This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.
Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980’s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1/N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N-1 masks. Vote-taking has recently been brought under the attention again for consideration in EUV lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations.
This paper provides a thorough experimental assessment of the implementation of vote-taking, and discusses its pro’s and con’s. Based on N=4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. Additionally, we found that blending different mask images brings clear benefit to the imaging, and provide experimental confirmation of improved local CDU and intra-field CDU, reduction of stochastic failures, improved overlay, ... Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner.
This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. While defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.
Assist features are commonly used in DUV lithography to improve the lithographic process window of isolated features under illumination conditions that enable the printability of dense features. With the introduction of EUV lithography, the interaction between 13.5 nm light and the mask features generates strong mask 3D effects. On wafer, the mask 3D effects manifest as pitch-dependent best focus positions, pattern asymmetries and image contrast loss. To minimize the mask 3D effects, and enhance the lithographic process window, we explore by means of wafer print evaluation the use of assist features with different sizes and placements. The assist features are placed next to isolated features and two bar structures, consistent with theN5 (imec iN7) node dimensions for 0.33NA and we use different types of off-axis illumination . For the generic iN7 structures, wafer imaging will be compared to simulation results and an assessment of optimal assist feature configuration will be made. It is also essential to understand the potential benefit of using assist features and to weigh that benefit against the price of complexity associated with adding sub-resolution features on a production mask. To that end, we include an OPC study that compares a layout treated with assist features, to one without assist features, using full-chip complexity metrics like data size.
EUV sources emit a broad band DUV Out-of-Band (OOB) light, in particular, in the wavelength range 100-400 nm. This can cause additional exposure of EUV resists made that are based on a ArF/KrF resist platform. This DUV light is partially suppressed while travelling through the optical path but a non-negligible part of it reaches wafer level and impacts imaging.
This is important for imaging at the edges of an image field when fields are printed very close to each other on the wafer (so-called butted fields, with zero field to field spacing). DUV light is reflected from the reticle black border (BB) into a neighboring exposure field on the wafer. This results in a CD change at the edges and in the corners of the fields and therefore has an impact on CD uniformity. Experimental CDU results are shown for 16 nm dense lines (DL) and 20 nm isolated spaces (IS) (N7 logic design features) in the fields exposed at 0 mm and 0.5mm distance on the wafer. Areas close to the edge of the image field are important for customer applications as they often contain qualification and monitoring structures; in addition, limited imaging capabilities in this area may result in loss of usable wafer space.
In order to understand and control OOB DUV light, it must be measured in the scanner. DUV measurements are performed in resist using a special OOB reticle coated with Aluminum (Al) having low EUV reflectance and high DUV reflectance. A model for DUV light impact on the imaging is proposed and verified. For this, DUV reflectance data is collected in the wavelengths range 100-400 nm for Al and BB and the ratio of reflectances of these materials is determined for assumed scanner and resist OOB spectra. Also direct BB OOB test is performed on the wafer and compared to Al OOB results. The sensitivity of 16 nm DL and 20 nm IS to OOB light is experimentally determined by means of double exposure test: a wafer with exposed imaging structures undergoes a second flood exposure from a DUV reflective material (Al or BB).
Finally, several OOB mitigation strategies are discussed, in particular, suppression of DUV light in the scanner (~3x improvement), recent successes of DUV suppression for 16 nm imaging resist (~1.8x improvement) and DUV reflectance mitigation in the reticle black border (~3.8x). An overview of OOB test results for multiple NXE systems will be shown including systems with new NXE:3350 optics with improved OOB suppression.
Photomask is at the heart of a lithographic scanner’s optical path. It cannot be left non-optimized from the imaging point of view. In this work we provide new insights on two critical aspects of EUV mask architecture: optimization of absorber for 16 nm half-pitch imaging and a systematic approach to black border EUV and DUV reflectance specifications. Good 16 nm imaging is demonstrated on ASML NXE:3300 EUV scanner. Currently a relatively high dose resist is used for imaging and the dose reduction is desired. Optimization (reduction) of absorber height and mask CD bias can allow for up to 30% dose reduction without essential contrast loss. Disadvantages of absorber height reduction are ~7 nm increase of best focus range through pitch and tighter absorber height mean to target and uniformity requirements. A disadvantage of a smaller reticle CD (down to 14 nm 1x) is manufacturing process uniformity over the reticle. A systematic approach of black border reflections impact on imaging is established. The image border is a pattern free dark area surrounding the image field and preventing exposure of the image field neighborhood on wafer. Currently accepted design of the black border on EUV reticle is an image border where the absorber and multilayer stack are etched down to the substrate and EUV reflectance is reduced to <0.05%. DUV reflectance of such a black border is about 5%. It is shown that a tighter DUV reflectance specification <1.5% is required driven by the impact of DUV reflections from the black border on imaging. NXE:3300 and NXE:3100 experimental imaging results are shown. The need of low DUV wavelength reflectance metrology (in the range 100-300 nm) is demonstrated using an estimated NXE scanner out-of-band DUV spectrum. Promising results of low DUV reflectance of the black border are shown.
The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.
The impact of various mask parameters on CDU combined in a total mask budget is presented, for 22 nm lines, for reticles used for NXE:3300 qualification. Apart from the standard mask CD measurements, actinic spectrometry of multilayer is used to qualify reflectance uniformity over the image field; advanced 3D metrology is applied for absorber profile characterization including absorber height and side wall angle. The predicted mask impact on CDU is verified using actual exposure data collected on multiple NXE:3300 scanners. Mask 3D effects are addressed, manifesting themselves in best focus shifts for different structures exposed with off-axis illumination. Experimental NXE:3300 results for 16 nm dense lines and 20 nm (semi-)isolated spaces are shown: best focus range reaches 24 nm. A mitigation strategy by absorber height optimization is proposed based on experimental results of a special mask with varying absorber heights. Further development of a black image border for EUV mask is considered. The image border is a pattern free area surrounding image field preventing exposure the image field neighborhood on wafer. Normal EUV absorber is not suitable for this purpose as it has 1-3% EUV reflectance. A current solution is etching of ML down to substrate reducing EUV reflectance to <0.05%. A next step in the development of the black border is the reduction of DUV Out-of-Band reflectance (<1.5%) in order to cope with DUV light present in EUV scanners. Promising results achieved in this direction are shown.
The first NXE3300B systems have been qualified and shipped to customers. The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33. It succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. Good overlay and imaging performance has been shown on the NXE:3300B system in line with 22nm device requirements. Full wafer CDU performance of <1.5nm for 22nm dense and iso lines at a dose of ~16mJ/cm2 has been achieved. Matched machine overlay (NXE to immersion) of around 3.5nm has been demonstrated on multiple systems. Dense lines have been exposed down to 13nm half pitch, and contact holes down to 17nm half pitch. 10nm node Metal-1 layers have been exposed with a DOF of 120nm, and using single spacer assisted double patterning flow a resolution of 9nm has been achieved.
Source power is the major challenge to overcome in order to achieve cost-effectiveness in EUV and enable introduction into High Volume Manufacturing. With the development of the MOPA+prepulse operation of the source, steps in power have been made, and with automated control the sources have been prepared to be used in a preproduction fab environment.
Flexible pupil formation is under development for the NXE:3300B which will extend the usage of the system in HVM, and the resolution for the full system performance can be extended to 16nm. Further improvements in defectivity performance have been made, while in parallel full-scale pellicles are being developed.
In this paper we will discuss the current NXE:3300B performance, its future enhancements and the recent progress in EUV source performance.
With the third generation EUV scanner, the NXE:3300B, it is expected that customers will move into volume
manufacturing of the devices and processes currently in development. The NXE:3300B has an NA of 0.33 and is
positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full
In this presentation we will demonstrate the imaging performance of the NXE:3300B EUV scanner. With the system
operating for almost a year now, we will show the main achievements, and present latest status on system performance,
with a focus on imaging of customer device applications.
For this, a wide range of features have been evaluated for lithographic performance across the field and across wafer. CD
performance for 22nm dense and isolated lines, 18nm and 16nm dense lines with off-axis illumination, 24nm contact
holes, as well as performance of customer device structures for 10nm node will be discussed and benchmarked against
the current ArF immersion capability.
The benefits of EUV for critical customer applications will be discussed, showing excellent imaging results for 2D
features and the extension capability to 13nm half pitch and beyond. This demonstrates the capability of EUV to bring
the single exposure resolution limit well below what can be achieved with complex multi-patterning techniques on ArFi.
The benefit of off-axis illumination usage for process window enhancement at challenging resolutions will be assessed.
The influence of mask 3D induced best focus difference on the overlapping depth of focus will also be addressed and
compared to current ArFi performance.
Furthermore a budget verification will be presented showing CD and contrast budgets for a selection of lithographic
features, such as 22nm dense and isolated LS. The contribution of the resist process and the mask will be discussed as
Finally an outlook will be given to future NA 0.33 systems with improved subsystem performance and full pupil
flexibility for off-axis illuminations.
All six NXE:3100, 0.25 NA EUV exposure systems are in use at customer sites enabling device development and cycles
of learning for early production work in all lithographic segments; Logic, DRAM, MPU, and FLASH memory. NXE
EUV lithography has demonstrated imaging and overlay performance both at ASML and end-users that supports sub-
27nm device work. Dedicated chuck overlay performance of <2nm has been shown on all six NXE:3100 systems.
The key remaining challenge is productivity, which translates to a cost-effective introduction of EUVL in high-volume
manufacturing (HVM). High volume manufacturing of the devices and processes in development is expected to be done
with the third generation EUV scanners - the NXE:3300B. The NXE:3300B utilizes an NA of 0.33 and is positioned at a
resolution of 22nm which can be extended to 18nm with off-axis illumination. The subsystem performance is improved
to support these imaging resolutions and overall productivity enhancements are integrated into the NXE platform
consistent with 125 wph. Since EUV reticles currently do not use a pellicle, special attention is given to reticle-addeddefects
performance in terms of system design and machine build including maintenance procedures.
In this paper we will summarize key lithographic performance of the NXE:3100 and the NXE:3300B, the NXE platform
improvements made from learning on NXE:3100 and the Alpha Demo Tool, current status of EUV sources and
development for the high-power sources needed for HVM.
Finally, the possibilities for EUV roadmap extension will be reviewed.
IC manufacturers have a strong demand for transferring a working process from one scanner to another. In an ideal transfer, a reticle set that produces devices within specification on a certain scanner has the same performance on another exposure tool. In real life, however, reticles employ optical proximity correction (OPC) which incorporates by definition the inherent optical fingerprint of a specific exposure tool and process. In order to avoid the additional cost of developing a new OPC model and acquiring a new reticle for each exposure tool, IC manufacturers therefore wish to 'match' the optical fingerprint of their scanners as closely as possible.
In this paper, we report on the matching strategy that we developed to perform a tool-to-tool matching. We present experimental matching results for several tool combinations at numerical apertures (NA) 0.75, 0.85 and 1.2. Matching of exposure tools is obtained by determining the sensitivities to scanner parameter variations like NA, Sigma, Focus Drilling, Ellipticity and Dose from wafer data and/or simulations. These sensitivities are used to calculate the optimal scanner parameters for matching the two tools.
IC manufacturers have a strong demand for transferring a working process from one scanner to another. In an ideal
transfer, a reticle set that produces devices within specification on a certain scanner has the same performance on another
exposure tool. In real life, however, reticles employ optical proximity correction (OPC) which incorporates by definition
the inherent optical fingerprint of a specific exposure tool and process. In order to avoid the additional cost of developing
a new OPC model and acquiring a new reticle for each exposure tool, IC manufacturers therefore wish to "match" the
optical fingerprint of their scanners as closely as possible.
In this paper, we report on the matching strategy that we developed to perform a tool-to-tool matching. We present
experimental matching results for several tool combinations at numerical apertures (NA) 0.75, 0.85 and 1.2. Matching of
two exposure tools is obtained by determining the sensitivities to scanner parameter variations like NA, Sigma, Focus
Drilling, Ellipticity and Dose from wafer data and/or simulations. These sensitivities are used to calculate the optimal
scanner parameters for matching the two tools.