Embedded image processing systems have to face heavier and heavier constraints in order to cope with the growing complexity of the algorithm and the increasing flexibility required by applications, while fulfilling more and more demanding implementation constraints. With a variety of target application profiles that include digital photography and remote sensing, the JPEG2000 standard is a typical example where complex and scalable techniques have to be implemented into highly integrated platforms. While the electronic system design community has pushed design-by-reuse as a key to manage complexity, providing a reusable hardware arhtiecture for JPEG2000 while preserving the high flexibility required by the wide application space is a major challenge. In this paper, we propose to address this issue by relying on a new class of synthesis tools: high-level synthesis (HLS) tools. HLS allows to specify hardware at a high abstraction level, where a variety of functional and architectural properties can be made customizable, and provides an automatic, constraint-driven architectural refinement flow that allows to generate a detailed register-transfer-level architecture from a behavioral (algorithmic-like) description of a component's behavior. Using a commercial HLS tool, we were able to generate a variety of JPEG2000-compliant discrete wavelet transform architectures, with varying hardware complexity and computation speed, from a single behavioral-level VHDL specification.