The present work describes a new architecture for a CDF(2,2) wavelet base. The proposed architecture is based on the recursive pyramid algorithm (RPA) and the multirate folding technique to obtain better performance. The used of folding and retiming techniques improves the area and speed-rate. In order to obtain a maximally fast structure, we have modified the initial architecture scheduling getting internal pipelining delays to minimize the logic depth to one adder.
Two different implementations using lifting scheme and polyphase decomposition are discussed. The lifting implementation requires approximately 52 % less hardware resources than the polyphase structure. Finally a comparative between our architecture and others folded architectures, which make all the computations into one filter bank, is presented. Our folded architecture reduces the number of registers and logic operators, increasing the frequency operation and minimizing the occupied area with the same throughput (one input / one output). Moreover, replicating delays block we can easily scale this architecture up. Our architecture performances an 87,5% hardware utilization.
KEYWORDS: Digital signal processing, Logic, Digital filtering, Wavelets, Discrete wavelet transforms, Very large scale integration, Structural design, Electronics engineering, Computer architecture, Time-frequency analysis
The present article describes a new high-efficient architecture for 1-D discrete wavelet packet transform (DWPT) base on lifting, folded and pipeline techniques, which makes possible to expand three completes levels. An architecture for a CDF(2,2) wavelet base is proposed. We have designed a filter bank using a lifting factorization for these coefficients and we have used an extension of the recursive pyramid algorithm (RPA) to obtain the three complete levels. We have pipelined our architecture to reach a maximally fast structure with only one logic operator in the critical path. Moreover, our architecture performances 75 % of hardware utilization for a DWPT realization. A comparative is presented between our DWPT architecture with others DWPT architectures. Our proposal lifting pipelined DWPT architecture is a maximally fast structure with only one logic operator in the critical path. Others DWPT architectures are based on memory access, that implies lower operation frequency and higher power consumption as our architecture.
KEYWORDS: Optical filters, Surgery, Wavelets, Finite impulse response filters, Field programmable gate arrays, Linear filtering, Discrete wavelet transforms, Medical imaging, Very large scale integration, Binary data
The present paper describes a new architecture for a Discrete Wavelet Packet Transform (DWPT) based on a folded Distributed Arithmetic (DA) implementation, which makes possible to expand two complete stages (4-subband DWPT). The proposed parameterized architecture can use different CDF wavelet coefficients with modified precision.
As the distributed arithmetic technique brings the possibility to make scalable designs, the proposed architecture can be easily parameterized. The data input and coefficient precision can be increased modifying the register size and the space memory, respectively. The number of coefficients can be change too increasing the memory and replicating the register structure. Our architecture uses only two FIR filters (high-pass and low-pass) that are folded to calculate various wavelet stages together in time. A discrete DWPT implementation using CDF(9/7) wavelet coefficients are implemented on VIRTEX-E1000-6 FPGA for different precisions. Finally, the use of both, the folding technique and the DA structure has offered a frequency operation of 75 MHz with 393 Flip-flop Slices (with 8 bits precision operation) on the FPGA.