Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning, and via fill material is required to protect etch stop layer and to provide excellent substrate reflectivity control. It also has to be completely removed after trench-etch. Organic bottom anti-reflective coating (BARC) material became a good candidate for 130nm via fill, but its shell defects in via following trench etch cause significant yield loss, especially in 90nm process and beyond with low-k dielectrics. A new SiO2 based via fill material matches plasma etch rate to SiOCH, SiOF, and SiO2 inter-layer dielectrics and prevents shell defects. It is applied by spin coating with standard bake and also highly absorbing to suppress substrate reflectivity. In this paper we integrate this SiO2 based material into 90nm Dual Damascene process. Topics such as performance in spin coating, trench lithography, plasma etching, and selective removal by wet clean will be discussed.
Extensive usage of Litho RET, Etch trimming and OPC techniques has become common practice in the integrated patterning flow for 90nm and beyond. In this paper, we will discuss our approach to use OPC for both etch and litho through-pitch bias correction for a 90nm contact layer. In stead of using conventional lumped model, [J.P. Stirniman, M.L. Rieger, SPIE Proc. Optical/Laser Microlithography X, Vol. 3051, p294, 1997], we introduced an alternative modeling approach to reduce our model correction into: Corrected Mask Layout = Tmask-1 (Toptical-1 (Tetch-1 (Design Layout) ) ). Post OPC checking using Synopsys SiVl platform shows that CD 3σ = 7.82nm of through-pitch OPC residual error. This study also shows that integrated patterning flow combined with LRC tools is useful to provide feedback to the designer and highlight some patterning process limitation that is design dependent.