This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI architecture for high
definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in
multi-resolution reference pixels, huge throughput and computation due to large search window are alleviated
considerably. Sixteen way parallel processing element arrays with configurable multiplying technologies achieve fast
search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three
hierarchical levels for sequential motion vector refinement. The modified algorithm reaches a good balance between
implementation complexity and search performance. Also, the logic circuit and on-chip SRAM consumption of the VLSI
architecture are moderate.