This paper presents the design and optimisation of three types of high Quality (Q) factor air suspended inductors
(symmetric (a), symmetric (b) and circular), using micro-electro-mechanical systems (MEMS) technology, for 10GHz to
20GHz frequency band. The geometrical parameters of inductor topology, such as outer diameter, the width of metal
traces, the thickness of the metal and the air gap, are used as design variables and their effects on the Q-factor and
inductance are thoroughly analysed. The inductor has been designed on high resistivity Silicon-on-Sapphire (SOS)
substrate in order to reduce the substrate loss and improve the Q factor. Results indicate that the proposed inductor
topology (symmetric (a)) has highest Q-factor with peak Q-factor of 192 at 12GHz for a 1.13nH inductance.
This paper presents the design and implementation of a fully on-chip wideband low noise amplifier (LNA) using 0.25-
micron Silicon-on-Sapphire (SOS) technology for the next-generation Square Kilometre Array (SKA) radio telescope
application. Ultra low noise and wideband operation are the principle design challenges in LNA for SKA application.
The proposed LNA design employs cascaded inductive degeneration architecture and achieves broadband matching by
using on-chip high quality factor (Q) SOS inductors inter-stage/intermediate LC matching circuit. Use of high Q
inductors results in low noise input matching circuit that enables the LNA to achieve the required minimum noise figure
(NF). The proposed LNA is a complete on-chip solution that achieves a NF from 0.57dB to 0.68dB over 1.1GHZ-band
with a minimum gain of 15.3dB. This design consumes only 40.78mW of power from a 2.5-V power supply.
This paper presents an optimised low-power low-phase-noise Voltage Controlled Oscillator (VCO) for Bluetooth
wireless applications. The system level design issues and tradeoffs related to Direct Conversion Receiver (DCR) and
Low Intermediate Frequency (IF) architecture for Bluetooth are discussed. Subsequently, for a low IF architecture, the
critical VCO performance parameters are derived from system specifications. The VCO presented in the paper is
optimised by implementing a novel biasing circuit that employs two current mirrors, one at the top and the other one at
the bottom of the cross-coupled complementary VCO, to give the exact replica of the current in both the arms of current
mirror circuit. This approach, therefore, significantly reduces the system power consumption as well as improves the
system performance. Results show that, the VCO consumes only 281μW of power at 2V supply. Its phase noise
performance are -115dBc/Hz, -130dBc/Hz and -141dBc/Hz at the offset frequency of 1MHz, 3MHz and 5MHz
respectively. Results indicate that 31% reduction in power consumption is achieved as compared to the traditional VCO
design. These characteristics make the designed VCO a better candidate for Bluetooth wireless application where power
consumption is the major issue.
This paper presents the design and implementation of an optimised MEMS-based reconfigurable VCO for a multi-standard
mobile terminal for GSM900, DCS1800 and WCDMA standards. In this VCO design, the passive components,
including inductors, capacitors and switches are replaced by MEMS components, to improve the system performance
and reduce the system power consumption. Moreover, a phase noise optimisation algorithm is also proposed to optimise
the VCO design for optimum system phase noise and minimum power consumption. Results show that a 50% reduction
of power consumption is achieved when the MEMS components are used instead of the passive components. A 31%
further reduction of power consumption is also achieved when the tail-current optimisation algorithm is applied. This
characteristic makes the VCO a better candidate for wireless communication applications where power consumption is
the major factor.
This paper presents the design and implementation of an intelligent data processing system for a wireless sensor node for healthcare application. The data processing system comprises of front-end sensors and a data acquisition (DAQ) system for signal processing. A smart property for the system has been developed so that it automatically selects the optimum method to 'condition' the biosignals, depending on the input channel requirements for better system accuracy. Moreover, it correspondingly selects an optimal sampling speed for each input channel to reduce the system power consumption, data storage and cost. Results show that a 47% reduction in power consumption is achieved and the aliasing error is reduced by 31% when the smart data processing architecture is used instead of traditional fix-rate data processing system.
Proc. SPIE. 5649, Smart Structures, Devices, and Systems II
KEYWORDS: Data acquisition, Control systems, Signal detection, Relays, Electronic filtering, Signal generators, Digital signal processing, Clocks, Error analysis, Application specific integrated circuits
This paper presents the application specific integrated circuit (ASIC) implementation of an intelligent controller for a reconfigurable data acquisition (DAQ) system. The DAQ system is employed in a digital relay for power system protection application. The controller is the intelligence behind the reconfigurable architecture. It continuously monitors the voltages and currents to detect the appearance of an abnormal condition on the power transmission network. Then it will send signals to adjust DAQ system sampling speed and filter cut-off frequency for properly detecting the fault location and properly analysing the fault. A novel approach to determine the line impedance angle has been proposed. This approach eliminates the square-root and arc-tan operations to reduce the cost of the semi-custom ASIC implementation of the intelligent controller. Analysis revealed that the intelligent controller achieved a maximum operating frequency of 100MHz, with 10ns critical path delay. The controller core utilises an area of 1.9mm<sup>2</sup>.
This paper presents a fully differential ultra low power successive approximation (SA) Analog-to-digital converter (ADC) for biomedical application. In order to reduce the system power consumption, the building block components of the SA ADC architecture has been optimised. In addition, the ADC the input voltage swing is scaled down to in order to reduce the slope gain error and the nonlinearity errors. The SA ADC has been implemented in Cadence Analog Design Environment using 0.18-micron CMOS technology. The designed SA ADC operates at a sampling rate of 200S/s at 3V power supply and consumes only 12µW of power at this frequency. The ADC standby power consumption is less than 1µW. The designed 16-bit ADC occupies an area of 0.1 mm<sup>2</sup> and is the smallest in size among its 16-bit counter parts reported in the literature. The proposed 16-bit ADC achieves the differential-non-linearity (DNL) and integral-non-linearity errors (INL) of ± 0.5 LSB and ± 0.3 LSB respectively.
This paper presents the performance analysis of different high-accuracy sample-and-hold circuit (SHC) techniques using CMOS technology. The paper begins with a detailed analysis of the major factors that limit the accuracy of a fundamental SHC. Then different techniques to implement high-accuracy SHCs are described. SHC employing transmission gate and SHC using feedback loop with compensation capacitor, as well as the fundamental SHC, were all implemented and tested and performance results demonstrate the superiority of each SHC schemes. For comparison reasons, the three SHCs were operated at a speed of 330 MHz. Results indicate that an increase of accuracy of 95% is achieved and the maximum sampling speed is increased by 15% when the SHC using feedback loop is used instead of the fundamental SHC. These characteristics make this device better candidate for many applications where speed and accuracy are the major factors.