A novel 16-channel optical backplane bus with volume holographic optical
elements (VHOEs), operating as diffraction grating beam alignment guides, was designed
and fabricated for a high-performance computing system multi-slot bus. These thin film
VHOEs were fabricated to diffract light beams for each bus slot into a glass wave-guiding
plate (refractive index 1.52) for total internal reflection to other slot positions. Slot-to-slot
optical alignment issues, including channel crosstalk and beam alignment tolerances, were
computer modeled to optimize a low cost and simple optical packaging structure. For each
slot position, a 4 × 8 element optical packaging plate was then fabricated to allow insertion
of 16 VCSELs and 16 Photodiodes, each in an individual TO-46 can.
Through the VHOE, the slot-to-slot fan-out received beam intensities were
experimentally measured for each of the 16 channels and found to be in the range of 90 &mgr;W
~ 150 &mgr;W. This 90 &mgr;W minimum fan-out power is 5dB greater than the receiver sensitivity
requirement. In this study, the maximum 10 Gbps single channel bandwidth was tested and
a 1.6 Gbps aggregate bandwidth was also demonstrated through a three slot 16-channel
optical backplane bus. This aggregate bandwidth was limited by an electronic element in
the receiver circuit (155 Mbps PD-TIA) and processor (100 Mbps FPGA). With the
system's measured optical isolation of greater than 80dB, and suitably fast receiver
electronics, simulation modeling indicates that Terabit per second bus data rates can be
achieved in inexpensive, mechanically robust and reliable form factors.
A 3-slot optical backplane bus demonstrator based on glass substrate with photopolymer volume gratings array (PVGA)
on top surface is built to allow 16 channels of data to be broadcast from central slot to two daughter slots or uploaded from
any daughter slot to central slot. VCSELs and photodetectors packaged in the form of TO-46 can are assembled on top of
each PVG and interleaved to reduce the crosstalk to below noise level. By carefully aligning the fabrication system, the
incident angle deviation from Bragg condition is reduced to below 0.1° to maximize optical power delivery. The
orientation and period of hologram fringes are uniform in the active area by collimating recording beams.
Above 4.8Gbps aggregated data transmission is successfully demonstrated using the multi-channel system. Three
computer mother boards using FPGA are made to verify the data transmission among the slots. Interface boards between
the FPGA boards and optical transceivers are designed and fabricated to separate the implementation of digital layer and
optical layer. Single channel transmissions with 3.2Gbps and even 10Gbps data rate are also tested with above 100uW
input power, showing the potential to improve the total two-way bandwidth to above 102.4Gbps. Alignment tolerance of
the optical interconnect system is investigated theoretically and experimentally. By analyzing the diffractive
characteristics, the bandwidth limit of the optical layer is determined to be in the order of Terahertz. Design and
fabrication issues are discussed for future optical backplane bus to make terahertz bandwidth into reality. Based on the
experiments for Bit-interleaved Optical Backplane bus and Multi-channel optical backplane bus demonstrators,
theoretical analysis of the bandwidth limit of the optical backplane bus using photopolymer volume gratings has been
Optical backplane bus based on glass substrate with volume holographic gratings on top surface possesses a great ability to broadcast information. This feature is utilized to accomplish a bit-interleaved optical interconnect system. In this system, each daughter board sends only one bit per round and the bit pulses from different boards can cascade in a designed series when the transmitters are distributed in an appropriate manner. In this way, even slow electronic chips can be coordinated to generate an aggregate bandwidth up to 10Gbps, which is impossible to achieve with a multi-drop electrical bus. Besides the benefits of high data rate and low crosstalk, such a bit-interleaved architecture provides a secure data storage method. Each daughter board only stores a quarter bits of any byte, so that no single board has the entire information and security is enhanced. Alignment tolerance and power budget of the proposed optical interconnect system is theoretically calculated and experimentally verified. With collimating lenses, the packing density of transceivers is more than 4/cm2, and thus the signal density can be above 40Gbps/cm2/board. The insertion loss due to misalignment and beam divergence is measured to be approximately 3dB. The bit error rate (BER) of 10Gbps receivers with -12dBm sensitivity is estimated to be below 10-12.
The primary technical challenge for optical backplanes involve the alignment and optical isolation of multiple data channels. Since most backplanes require data transfer rates greater than a single optical channel can costeffectively provide, multiple data channels is the common solution for higher aggregate transfer rates. Established optical alignment and isolation techniques include spatial separation of optical channels, use of lensing elements to focus specific transmitter outputs to specific receiver areas, use of differing wavelengths for adjacent channels with appropriate frequency filtering on receivers, and the use of "light guide tubes" for each channel. This presentation will examine another promising option, the use of "matched" Holographic Optical Elements (HOEs) to provide both cross channel optical isolation and to significantly relax traditional optical alignment requirements. Matched HOEs can both induce upon a transmitted optical stream, and then filter upon a received optical stream, a number of distinguishing characteristics such as wavelength, polarization, phase, and amplitude. Thus the use of a unique "matched HOE" pair with each transmitterreceiver pair of multiple optical data channels can provide an efficient mechanism to isolate individual data streams even when they may be physically coincident, such as in a length of fibre optic or when multiple free space data transmitters illuminate several channel's receiver elements. Thus, the alignment issue is relaxed from the usual constraint of attempting to physically separate channels to one where, as long as the receiver is within the optical cone of it's matched transmitting element, cross channel interference can be effectively eliminated.
As multiprocessing comes into the mainstream, the board-to-board interconnects become even more critical. In a shared-memory multiprocessing system, the shared bus topology is the preferred interconnect scheme because its broadcast nature can be effectively utilized to reduce communication latency, lessen networking complexity, and support cache coherence. In the electrical domain, however, a major performance bottleneck is anticipated due to the restricted bus bandwidth. In this paper, an innovative architecture, optical centralized shared bus, is proposed for use in the multiprocessing systems. This architecture utilizes the terascale bandwidth capacity of substrate-guided optical interconnects, while at the same time, retaining the essential merits of the shared bus topology. Thus, a smooth migration with substantial multiprocessing performance improvement is expected. A conceptual emulation of the shared-memory multiprocessing scheme is demonstrated on a generic PCI subsystem with an optical centralized shared bus. The objective of this effort is to prove the technical feasibility from the architecture standpoint.