In recent years semiconductor manufacturers have increasingly employed deep through-silicon via (TSV) at the front end of line (FEOL) process steps, combined with using an increased number of multilevel, three-dimensional (3D) layers with different material stack at the back end of line (BEOL) process steps. This increased usage results in enhanced requirements for 3D feature characterization during the process development steps, as well as with monitoring and failure analysis during production.
Traditionally, deep TSV features during the FEOL are analyzed by cleaving (breaking) the wafers and observing the cross section. At the BEOL, focused ion beam (FIB) cross section and etch back or chemical mechanical polishing (CMP) of layer-by-layer are used to characterize the 3D multilevel layers. Both methods result in a slow turnaround time (TAT), but most importantly, cross section analysis only gives two-dimensional (2D) information about 3D multilevel structure and can miss abnormalities. Etch back or CMP has relatively low quality, accuracy, and repeatability and results in full wafer scrap.
Inline Xe plasma FIB (PFIB) has become an important tool for 3D feature characterization and failure analysis in the chip manufacturing production line. Layer-by-layer excavation (also known as delayering) of a specific site provides enhanced metrology and reconstruction of complete 3D features. Thus, manufacturers can identify process abnormalities of the complete structure. Moreover, inline delayering, combined with cross sectioning of specific sites, enhances the TAT. The wafer can return to production for further analysis, and manufacturers can study the effects on different steps.
In the semiconductor manufacturing process, defects often occur due to a marginal process window that affects the lithography and etch processes. These defects can result in bridging patterns and overlay issues, which consequently cause electrical shorts and partially etched vias producing electrical opens. SEM tools are used to find electrical failures through voltage contrast techniques. Manufacturers who fabricate with older process technology nodes often need to use their tool set more efficiently. This paper demonstrates an application of conventional SEM review with image to golden reference image inspection capabilities in Automatic Process Inspection (API ) mode to perform electrical inspections of die features.
This paper details how to use a SEM review tool to detect systematic electrical defects. This methodology can prove beneficial while monitoring and developing patterning techniques for a specific design rule by catching electrical shorts and opens that are more visible at a lower resolution inspection used in process monitoring. Outcomes of this effort show that conventional review SEM techniques, using known areas prone to process inconsistencies derived from features pushing the design rule, have the capability to effectively and efficiently monitor fabrication process while implemented in a production setting at process nodes between 100 to 200 nm. Using e-beam review tools offers several advantages and disadvantages. This paper demonstrates that by using a SEM review tool and selecting die locations for imaging that are more likely to fail electrically, manufacturers can use SEM automatic review capabilities more effectively and efficiently. The application developed may also be applied in fabrication facilities that have limited yield monitoring capacity.
This paper is a result of collaboration between Applied Materials and Microchip Technology Inc.