As one of the most promising next generation lithography technologies, multiple patterning lithography (MPL) plays an important role in the attempts to keep in pace with 10 nm technology node and beyond. With feature size keeps shrinking, it has become impossible to print dense layouts within one single exposure. As a result, MPL such as double patterning lithography (DPL) and triple patterning lithography (TPL) has been widely adopted. There is a large volume of literature on DPL/TPL layout decomposition, and the current approach is to formulate the problem as a classical graph-coloring problem: Layout features (polygons) are represented by vertices in a graph G and there is an edge between two vertices if and only if the distance between the two corresponding features are less than a minimum distance threshold value dmin. The problem is to color the vertices of G using k colors (k = 2 for DPL, k = 3 for TPL) such that no two vertices connected by an edge are given the same color. This is a rule-based approach, which impose a geometric distance as a minimum constraint to simply decompose polygons within the distance into different masks. It is not desired in practice because this criteria cannot completely capture the behavior of the optics. For example, it lacks of sufficient information such as the optical source characteristics and the effects between the polygons outside the minimum distance. To remedy the deficiency, a model-based layout decomposition approach to make the decomposition criteria base on simulation results was first introduced at SPIE 2013.1 However, the algorithm1 is based on simplified assumption on the optical simulation model and therefore its usage on real layouts is limited. Recently AMSL2 also proposed a model-based approach to layout decomposition by iteratively simulating the layout, which requires excessive computational resource and may lead to sub-optimal solutions. The approach2 also potentially generates too many stiches. In this paper, we propose a model-based MPL layout decomposition method using a pre-simulated library of frequent layout patterns. Instead of using the graph G in the standard graph-coloring formulation, we build an expanded graph H where each vertex represents a group of adjacent features together with a coloring solution. By utilizing the library and running sophisticated graph algorithms on H, our approach can obtain optimal decomposition results efficiently. Our model-based solution can achieve a practical mask design which significantly improves the lithography quality on the wafer compared to the rule based decomposition.
As we advances into 14/10nm technology node, single patterning technology is far from enough to fabricate the
features with shrinking feature size. According to International Technology Roadmap for Semiconductors in
2011,1 double patterning lithography is already available for massive productions in industry for sub-32nm half
pitch technology node. For 14/10nm technology node, double patterning begins to show its limitations as it uses
too many stitches to resolve the native coloring conflicts. Stitches will increase the manufacturing cost, lead
to potential functional errors of the chip, and cause the yield lost. Triple patterning lithography and E-Beam
lithography are two emerging techniques to beat the diffraction limit for current optical lithography system. In
this paper, we investigate combining the merits of triple patterning lithography and E-Beam lithography for
standard cell based designs. We devise an approach to compute a stitch free decomposition with the optimal
number of E-Beam shots for row structure layout. The approach is expected to highlight the necessity and
advantages of using hybrid lithography for advanced technology node.
At the 7 nm technology node, the contact layers of integrated circuits (IC) are too dense to be printed by single exposure lithography. Block copolymer directed self-assembly (DSA) has shown its advantage in contact/via patterning with high throughput and low cost. To pattern contacts with DSA, guiding templates are usually printed first with conventional lithography, e.g., 193 nm immersion lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of controlling the DSA patterns inside, which have a finer resolution than the templates. The DSA contact pitch depends on the chemical property of block copolymer and it can be adjusted within a certain range under strong lateral confinement to deviate from the natural pitch. As a result, different patterns can be obtained through different parameters. Although the guiding template shapes can be arbitrary, the overlay accuracy of the contact holes patterned are different and largely depend on the templates. Thus, the guiding templates that have tolerable variations are considered as feasible, and those have large overlays are considered as infeasible. To pattern the contact layer in a layout with DSA technology, we must ensure that all the DSA templates in the layout are feasible. However, the original layout may not be designed in a DSA-friendly way. Moreover, the routing process may introduce contacts that can only be patterned by infeasible templates. In this paper, we propose an optimization algorithm that optimize the contact layer for DSA patterning in 1D standard cell design. In particular, the algorithm modifies the layout via wire permutation technique to redistribute the contacts such that the use of infeasible templates is avoided and the feasible patterns that with better overlay control are favored. The experimental result demonstrate the ability of the proposed algorithm in helping to reduce the design and manufacturing cost of a DSA-enabled process at 7 nm technology node.
With the minimum feature size keeps shrinking, there are increasing difficulties to print these small features using one exposure (LE) or double exposures (LELE). To resolve the inherent physical limitations for current lithography techniques, triple patterning lithography (LELELE) has been widely recognized as one the most promising options for 14/10nm technology node. For triple patterning lithography (TPL), the designers are more interested in finding a decomposition with none of the three masks overwhelms the other. This color balancing issue is of crucial importance to ensure that consistent and reliable printing qualities can be achieved. In our previous work,18 a simple color balancing scheme is proposed to handle designed without stitches, which is not capable of handling complex designs with stitches. In this paper, we further extend the previous approach to be able to simultaneously optimizing the number of stitches and balancing the color usage in the three masks. This new approach is very efficient and robust, and guarantees to find a color balancing decomposition while achieving the optimal number of stitches. For the largest benchmark with over 10 million features, experimental results show that the new approach achieves almost perfect color balancing with reasonable runtime.
As the current 193nm ArF immersion lithography technology is approaching its bottleneck, multiple patterning techniques have to be introduced to fulfill the process requirements in the sub-20nm technology node. Among all different patterning techniques, triple patterning lithography (TPL) is one of the major options for 14 nm or 10 nm technology node, which has a substantial requirement on process control and cost control at the same time. Patterning decomposition is the key step for the success of TPL. In the conventional TPL lithography, a constant spacing distance dmin is used to determine whether two nearby features should be on the same mask. However, in reality, the no-print and the best-print scenarios can never be separated by a clear constant number. Indeed, the decomposition criteria is closed related to lithography printing parameters, pattern types, and geometry distances. The conventional spacing rule with a constant number is way too simple. In this paper, we re-evaluate the conventional minimum spacing rule and utilize a local pattern cost model to evaluate our previous optimal TPL algorithm. Given a user specified local pattern aware cost model, our algorithm can easily embed the model into our formulation and compute an optimal solution. This demonstrates the extendability and robustness of our previous TPL algorithm.