This paper presents the improved readout system of multi-level signal waveform modulation read-only disk. The
experimental results show the performance of the improved readout system is better than that of the former system.
Multilevel storage is the easiest two-dimensional storage technology. On the basis of recording and read-out optical
system of Digital Versatile Disc (DVD), by the method of multilevel run-length coding, the storage capacity can be
increased by 60 percent of DVD9's, reaching 14 Giga Bytes.
In order to meet the requirement of a 10-4 raw Bit Error Rate (BER) of data readout, this paper presents a method of
multilevel run-length coding with changeable level numbers. This method can take advantage of run-length redundancy
to the utmost and reduce Inter-Symbol Interference (ISI) caused by multilevel run-length. Multilevel run-length coding
uses the method of two steps modulation. This paper introduces a coding method of DK (1, 9) and R=1 code rate.
Realized by Pulse Width Modulation, multilevel run-length modulation coding with changeable level has good
symmetry. Its readout characteristics are the same as that of DVD with normal run-length modulation, therefore the
servo control system needn't be changed. Also the signal can be recognized in two aspects respectively, run-length and
level. In the sample disc, average raw BER in the two aspects is less than 10-3.
Multilevel run-length modulation coding could be applied in various systems of run-length modulation coding. On the
basis of the structure and characteristics of the primitive system, the comprehensive efficiency of coding could be
increased by 33 to 50 percent.
Our team have proposed and implemented a new type of multi-level DVD, which features in using the waveform to
differentiate levels. Servo accuracy is an important issue for an optical disk system, since it can directly influence the
quality of readout signal. This paper analyses the influence of servo error on the readout signal for our multi-level DVD
using numerical simulation. A readout model is established, where focus error (FE) and tracking error (TE) is introduced.
A new parameter, waveform deviation, is proposed to quantitatively evaluate the influence. Simulation results show that
the influences of TE/FE on readout signal are similar. Each of them will shrink the dynamic range of readout signal.
When TE/FE exceeds a threshold, the waveform deviation will increase sharply.
The Radio Frequency (RF) signal of the Multi-Level Run-Length-Limited (ML-RLL) read-only disc is different from
that of DVD, so the readout system of the ML-RLL read-only disc is built specially. The readout system of the ML-RLL
read-only disc can realize servo control, RF signal readout and so on. The readout system consists of Digital Versatile
Disc (DVD) traverse, analog front-end and digital processing part. Analog front-end can realize front-end amplification
of the output signal of the optical pick-up and power drive of mechanism. Digital processing part mainly consists of
digital circuits, which functions are the servo controlling, demodulation and decoding of RF signal, general control and
so on. The whole system is implemented on two Field Programmable Gate Array (FPGA) chips and the experimental
results show a good performance. We tested the important signals, and experimental results are also given to verify the
performance of this development platform, which meets the controlling and detecting requirements to multi-level
read-only disc completely. The Bit Error Rate (SER) can achieve below 10-4.
In this paper, we discuss a bus sharing architecture to implement a minimal unit for DVD jukebox. The bandwidth of host channel is usually tens times of the data rate of one disk. We integrate several DVD-ROM by sharing one ATA bus. It can fill the host channel by data transfer phase as much as possible. The shared ATA bus can be one or more to reach the bandwidth of host. And a queue and buffer algorithm to improve the performance of response time and synchronize is also introduced.
After analyzing the system architecture and the routine design method of a SCSI controller, one novel design project for the SCSI controller is proposed on the basis of SOPC and soft processor IP core technology. The NIOS soft processor IP core is chosen as the center controller in the application system. Except for NIOS processor, most of the peripherals around the SCSI module, including DMA data channel and data cache control logic, are integrated into one FPGA chip. Comparing with the routine design method, the new project has better features in the expansibility, scalability, improvability and in-system programmability. As an instance, the SCSI to ATA interface system based on SOPC is introduced and given the satisfying I/O speed test results.