Correlation of resist modeling of printed features with lithographic data is a necessary part of developing new lithographic processes. Recently, we have found a case in which the most advanced resist types sometimes show better behavior than expectations from optical simulation in terms of dose latitude, MEEF (mask error enhancement factor), and even CD variation through different pitches. This superior resist performance may allow greater margin for error in each component, such as mask, scanner, and metrology in very low-k1 lithography.<p> </p> On the other hand, since the resist pattern CD for the most advanced resist is very much different from the prediction of optical simulation, it is a challenge to build OPC models using the exposure result with the resist. In order to solve this issue, we have tried to use several litho parameters to reduce the gap between optical simulation and resist CDs for OPC modeling. In this paper we discuss the effect of the parameters to reduce the gap between optical model and actual resist behavior with keeping superior performance as much as possible. The method we mention may be a key to use the most advanced resist in near future. As a result the life of ArF immersion lithography in the critical layer would be extended than we expect today.
Due to the importance of errors in lithography scanners, masks, and computational lithography in low-k1 lithography,
application software is used to simultaneously reduce them. We have developed “Masters” application software, which is
all-inclusive term of critical dimension uniformity (CDU), optical proximity effect (OPE), overlay (OVL), lens control
(LNS), tool maintenance (MNT) and source optimization for wide process window (SO), for compensation of the issues
on imaging and overlay.
In this paper, we describe the more accurate and comprehensive solution of OPE-Master, LNS-Master and SO-Master
with functions of analysis, prediction and optimization. Since OPE-Master employed a rigorous simulation, a root cause
of error in OPE matching was found out. From the analysis, we had developed an additional knob and evaluated a proof-of-
concept for the improvement. Influence of thermal issues on projection optics is evaluated with a heating prediction,
and an optimization with scanner knobs on an optimized source taken into account mask 3D effect for obtaining usable
process window. Furthermore, we discuss a possibility of correction for reticle expansion by heating comparing
calculation and measurement.
Source mask optimization (SMO) is widely used to make state-of-the-art semiconductor devices in high-volume manufacturing. To realize mature SMO solutions in production, the Intelligent Illuminator, which is an illumination system on a Nikon scanner, is useful because it can provide generation of freeform sources with high fidelity to the target. Proteus SMO, which employs co-optimization method and an insertion of validation with mask three-dimensional effect and resist properties for an accurate prediction of wafer printing, can take into account the properties of Intelligent Illuminator. We investigate an impact of the source properties on the SMO to pattern of a static random access memory. Quality of a source made on the scanner compared to the SMO target is evaluated with in-situ measurement and aerial image simulation using its measurement data. Furthermore, we discuss an evaluation of a universality of the source to use it in multiple scanners with a validation and with estimated value of scanner errors.
The k1 factor continues to be driven downward in ArF immersion lithography, even below its limit from optical theory, using various lithographic techniques such as combination of Source and Mask Optimization (SMO) and multiple patterning. Such a low k1 factor tends to lead to extremely high sensitivity tp imaging parameters such as aberrations, distortion, illumination pupilgram shape, dose, focus, etc. Therefore, fast, precise and stable settings of these parameters are crucial to make such hyper low k1 lithography practical. We introduce various kinds of imaging application tools and technique, which we have been developing, to support the imaging parameter settings and control. The application tools cover illumination pupilgram adjustment for freeform illumination, automatic aberration control, and thermal aberration parameter settings.
Thermal aberration becomes a serious problem in the production of semiconductors for which low-k1 immersion lithography with a strong off-axis illumination, such as dipole setting, is used. The illumination setting localizes energy of the light in the projection lens, bringing about localized temperature rise. The temperature change varies lens refractive index and thus generates aberrations. The phenomenon is called thermal aberration. For realizing manufacturability of fine patterns with high productivity, thermal aberration control is important. Since heating areas in the projection lens are determined by source shape and distribution of diffracted light by a mask, the diffracted pupilgram convolving illumination source shape with diffraction distribution can be calculated using mask layout data for the thermal aberration prediction. Thermal aberration is calculated as a function of accumulated irradiation power. We have evaluated the thermal aberration computational prediction and control technology “Thermal Aberration Optimizer” (ThAO) on a Nikon immersion system. The thermal aberration prediction consists of two steps. The first step is prediction of the diffraction map on the projection pupil. The second step is computing thermal aberration from the diffraction map using a lens thermal model and an aberration correction function. We performed a verification test for ThAO using a mask of 1x-nm memory and strong off-axis illumination. We clarified the current performance of thermal aberration prediction, and also confirmed that the impacts of thermal aberration of NSR-S621D on CD and overlay for our 1x-nm memory pattern are very small. Accurate thermal aberration prediction with ThAO will enable thermal aberration risk-free lithography for semiconductor chip production.
Source mask optimization (SMO) is widely used to make state-of-the-art semiconductor devices in high volume manufacturing. To realize mature SMO solutions in production, the Intelligent Illuminator, which is an illumination system on Nikon scanner, is useful because it can provide generation of freeform sources with high fidelity to the target. Proteus SMO, which employs co-optimization method and an insertion of validation with mask 3D effect and resist properties for an accurate prediction of wafer printing, can take into account the properties of Intelligent Illuminator. We investigate an impact of the source properties on the SMO to pattern of a static-random access memory. Quality of a source made on the scanner compared to the SMO target is evaluated with in-situ measurement and aerial image simulation using its measurement data. Furthermore we discuss an evaluation of a universality of the source to use it in multiple scanners with a validation with estimated value of scanner errors.
This work describes freeform source optimization considering mask error enhancement factor (MEEF), optical proximity effect (OPE), process window, and hardware-specific constraints. Our algorithm allows users to define maximum allowed MEEF and OPE error as constraints without defining weights among the metrics. We also consider hardware specific constraints, so that the optimized source is suitable to be realized in Nikon’s Intelligent Illumination hardware. Our approach utilizes a global optimization procedure to arrive at a freeform source shape solution, and since each source grid-point is assigned as variable, the source solution encompasses the maximum amount of degrees of freedom.
Due to the promising development status of EUVL as a practical lithography technology for the 2x-nm node, we are
continuing to evaluate its process liability using the EUV1 at Selete, which has an Off-Axis illumination capability. The
resolution limit of the EUV1 for L&S patterns is currently 18 nm for dipole illumination, and 16 nm for aggressive
dipole illumination. This study examined the critical points of EUVL for device manufacturing through wafer processes.
The yield obtained from electrical measurements indicates the maturity of the technology, including the resist process,
the tool, and the mask. Optimization of the resist and RIE processes significantly improved the yield. The final yields
obtained from electrical measurements were 100% for hp 30 nm, 70% for hp 28 nm, and 40% for hp 26 nm. These
results demonstrate EUV lithography to be a practical technology that is now suitable for 2x nm semiconductor
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm<sup>2</sup> was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
When a thinner absorber mask is applied to extreme ultraviolet (EUV) lithography for chip production, it becomes essential to a introduce light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. In this paper, we evaluate the leakage of both EUV and out-of-band from light-shield border and clarify the dependence of lithographic performance on light-shield border structure using a small field exposure tool with/without spectral purify filter (SPF). Then we evaluate the lithographic performance of a thin absorber EUV mask with light-shield border of the etched multilayer type and demonstrate the merit of its structure using a full-field scanner operating under the currently employed condition of EUV source in which SPF is not installed.
The impact of an EUV mask absorber defect with pattern roughness on lithographic images was studied. In order to reduce systematic line width roughness (LWR) of wafer printed patterns, the mask making process was improved; and in order to reduce random LWR, low line-edge roughness resist material and a critical dimension averaging method of multiple-exposure shots were introduced. Then, by using a small field exposure tool, a mask-induced systematic printed LWR was quantified and estimated at 32-nm half-pitch and 28-nm half-pitch. The measurement results of the critical mask absorber defect size were compared with the simulation, and the results were then discussed.
When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV
light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask
with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this
paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched
multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.
We are focusing on the establishment of a flare correction technique for half pitch (HP) 22-nm generation in Extreme
Ultra Violet Lithography (EUVL). However, there are some difficulties in the areas of flare calculation and edge biasing,
associated with flare correction because of the tighter CD control requirements. In our previous work, we investigated
the feasibility of an improved flare calculation and a new way of edge biasing. For the flare calculation, we adopted a
short-range flare kernel method, which calculates short-range flare using a fine mesh only at the edges of patterns that
require correction. From the simulation and experimental results of this method, we confirmed that it can calculate flare
value accurately in a reasonable runtime. On the other hand, since the edge biasing has pattern dependency the work has
to be customized accordingly, and that can lead to labor intensive task of pattern-dependent biasing. To address this
problem, we began to explore the usefulness of model-based flare correction that has been improved where it can
modulate the aerial image according to the flare effect during model-based OPC.
For this work, we prepared a test mask containing line-and-space (L/S) patterns of several pitches with different flare
levels. We then evaluated the accuracy of the model-based flare correction by simulating the corrected L/S patterns using
a rigorous lithography simulation with 3-D mask stack structure. As a result, the CD error range was found to be from - 1.56 to 1.12 nm, which is within ±2 nm (±10 % of the minimum target CD). It is thus concluded that the model-based
flare correction can deliver high accuracy results even where OPCs are also involved.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
Extreme ultraviolet lithography (EUVL) is one of the most promising candidates for the next-generation lithography. For
the adoption of EUVL, however, there are some technological issues to be solved. One of the critical issues is flare
which is an undesirable scattered light that reduces the aerial image contrast leading to a reduction in the process window
such as exposure latitude. Therefore, new methods to compensate for the anticipated flare effect have to be devised.
At Selete, flare correction based on a flare point-spread function (PSF) is investigated. We succeeded in achieving a CD
control of within a few nm over various pattern densities for the half-pitch (HP) 32-nm node.
However, our estimation shows that the previous flare correction scheme could not meet the accuracy criteria of flare
computation for HP 22-nm node. Therefore, we have modified the flare correction flow to implement a variable gridding
for pattern-density calculation. The variable gridding based on the shape of a PSF enables highly accurate flare
calculation within a reasonable runtime.
Furthermore, we will use model-based OPC for HP 22-nm node, whereas we normally use rule-based OPC for HP 32-
nm node. This is because the lithography process is reaching the low k1 regime.
In this work, we investigate the feasibility of model-based OPC incorporating flare correction.
Impact of EUV mask absorber defect with pattern-roughness on lithographic images was studied. In order to reduce
systematic line width roughness (LWR) of wafer printed pattern, mask making process was improved; and in order to
reduce random LWR, low line edge roughness (LER) resist material and a CD averaging method of multiple exposure
shots were introduced. Then by using a Small Field Exposure Tool (SFET), mask induced systematic printed LWR was
quantified and estimated at 32nm HP and 28nm HP. The measurement results of the critical mask absorber defect size
were compared with simulation; and the results are then discussed.
The Selete full-field EUV exposure tool, EUV1, manufactured by Nikon, is being set up at Selete. Its lithographic performance was evaluated in exposure experiments with a static slit using line-and-space (L&S) patterns, Selete Standard Resist 03 (SSR3), a numerical aperture of 0.25, and conventional illumination (=0.8). The results show that 25-nm L&S patterns were resolved. Dynamic exposure experiments demonstrate that the resolution is 45 nm across the exposure field. The CD uniformity across a shot is 3 nm. Evaluation of the overlay performance of the EUV1 using alignment marks on a processed wafer revealed the repeatability to be better than 1 nm. The overlay accuracy obtained with enhanced global alignment was less than 4 nm (3) after linear correction. These results show that the EUV1 has attained the quality level of a typical alpha-level lithography tool and is suitable for test site verification.
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
At Selete, correction for flare based on a flare point-spread function (PSFF) is investigated. We divide a layout into a grid
and calculate pattern density for each grid square, obtaining a density array as an approximation to the layout aerial
image. Then, the density array is convolved with the PSFF to create an array of flare values. Using this flare-value array,
we resize the layout.
In the above correction flow, size of a grid square of density array and a selection of an approximate function of the PSFF
have a great influence on the accuracy of flare value computation.
In this study, correction for flare was applied to the fabrication of several test masks using the real PSFF obtained from a
full-field step-and-scan exposure tool called EUV1. We report on the optimization of size of grid square, on a suitable
approximation model of PSFF, and on feedbacks from exposure experiments.
Since the k1 factor is much larger in extreme-ultraviolet lithography (EUVL) than in optical lithography, optical
proximity correction (OPC) should be much simpler for patterns on EUVL masks than for those on advanced
photomasks. This will facilitate the fabrication of complex device patterns with EUVL. In this study, static
random-access memory (SRAM) cell patterns for the half-pitch (hp) 32- and 45-nm nodes were fabricated using two
EUV exposure tools (SFET, EUV1), and their fidelity was evaluated. The levels of SRAM patterns were isolation, gate,
contact, and metal. The size of the SRAM unit cell was 0.191 μm<sup>2</sup> for the hp 45-nm and 0.097 μm<sup>2</sup> for the hp 32-nm
patterns. Most of the experiments employed SSR2, a high-resolution EUV resist. The high performance of the SFET and
SSR2 enabled hp 45-nm SRAM patterns to be fabricated faithfully. However, some of the hp 32-nm patterns deviated
from the mask patterns. To determine the causes of this degradation, we made a simulation analysis using the Sentaurus
Lithography simulator. The main cause of the degradation was found to be resist blur. When we used MET-2D resist,
which has a relatively large resist blur, the degradation became quite severe. Although the resist blur for SSR2 is about
10 nm, it is not small enough for the hp 32-nm SRAM patterns, especially for the gate and metal levels. It is necessary to
reduce resist blur to improve the fidelity for this pattern size. Simulation results indicated that resist blur should be
reduced to about 5 nm for hp 22-nm node device patterns.
The effect of mask absorber thickness on defect printability in EUV lithography was studied. In case of very thin
absorber, when used for EUVL mask, it became necessary to set specifications for mask defects for the
manufacturability of ULSI devices because mask absorber thickness could impact defect printability. We prepared
programmed mask defects of LR-TaBN absorber with various thicknesses. We then investigated defect printability of
thin absorber mask with Small Field Exposure Tool (SFET) by comparing the data with simulation results.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
The Selete full-field EUV exposure tool, the EUV1, was manufactured by Nikon and is being set up at Selete. Its
lithographic performance was evaluated in exposure experiments with a static slit using line-&-space (L&S) patterns,
Selete Standard Resist 03 (SSR3), an NA of 0.25, and conventional illumination (σ = 0.8). The results showed that 25-
nm L&S patterns were resolved. Dynamic exposure experiments showed the resolution to be 45 nm across the exposure
field and the CD uniformity across a shot to be 3 nm, also 26-nm L&S patterns were resolved.
Overlay performance of the EUV1 was showed as processed wafer mark alignment, the repeatability was under 1nm.
Overlay accuracy using EGA (Enhanced Global Alignment) was below 4nm at the 3-sigma after liner correction. These
results were good enough for an alpha-level lithography tool and test site verification.
The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very
thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area
on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and
fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we
demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).
The effects of mask absorber thickness on printability in EUV lithography was studied from the viewpoint of
lithographic requirements which can give high imaging contrast and reduce shadowing effect. From lithography
simulation, optimum thickness range of mask absorber (LR-TaBN) for exposure latitude was predicted, and the effect
of absorber thickness on MEF and H-V (Horizontal - Vertical) printed CD difference was determined using resist blur
model. From printability experiments with a Small Field Exposure Tool (SFET) and with high resolution resist,
optimum thickness of LR-TaBN absorber was demonstrated. When thinner absorber mask is employed in EUVL for
ULSI chip production, it becomes necessary to introduce EUV light shield area in order to suppress the leakage of EUV
light from neighboring exposure shots. Resist pattern CD change from the neighboring exposure shots was estimated
by lithography simulation.
The effects of aberration and flare on the lithographic performance of the EUV small-field exposure tool (SFET)
were evaluated. Simulation results indicated that the effect of aberration on the image contrast of line-and-space (L&S)
patterns should be small. In exposure experiments, 26-45-nm L&S patterns were successfully fabricated under annular
illumination (σ=0.3/0.7). A key factor limiting resolution should be resist performance. Simulation results also indicated
that the astigmatic aberration could produce a focal shift of about 60 nm between horizontal and vertical L&S patterns.
The experimentally obtained focus shift agreed well with the simulation results. Dense 32-45-nm contact-hole (C/H)
patterns were also successfully fabricated under annular illumination (σ=0.3/0.5). Due to astigmatic aberration, the C/H
patterns were deformed at defocused positions, but they were almost circular at the best focus position. The flare of the
projection optics measured by the Kirk method was 11% over a flare range of 1-100 μm. The effects of the 11% flare
were evaluated using dark- and bright-field 32-nm L&S patterns. It was found that the top loss and line-width roughness
(LWR) of the resist were larger for bright-field than for dark-field patterns. To reduce the impact of flare, we need EUV
resists that are more robust with regard to flare. A comparison of the measured point spread function (PSF) of the flare
and the calculated PSF revealed good agreement for long-range flare but some difference for short-range flare.
We have installed a small-field exposure tool (SFET) manufactured by Canon and EUVA with a discharge-producedplasma
EUV source that employs Xenon gas. We investigated how the performance of the source affects lithographic
performance. Electrode life has relation to the illumination uniformity of the exposure field on wafer surface. Also
source power at the wafer surface has relation to the electrode life. Electrode life makes EUV power decreasing and
larger illumination uniformity number. We examine the pupilgram test using high sensitivity resist. Actual pupil fill
shape was observed and there was non-uniform distribution. Pupil fill shape was changed after exchanging electrode,
also resist CD bias between parallel and horizontal line of the field. That was comparable to the simulation result.
The source electrode requires periodic replacement, which impacts not only the performance of the source, but also the
lithographic performance of the tool, such as the CD of resist patterns.
Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal
with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with
proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist
performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be
6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level
was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from
the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch
patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a
σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask
CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD,
we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD
mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance
up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In
a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled
off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that
aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results
yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This
research was supported in part by NEDO.
The impact of mask absorber properties on printability in EUV lithography was studied from the viewpoint of
lithographic requirements which can give high imaging contrast and reduce the shadowing effect. By using the
refractive indices of the elements and compounds employed as absorbers, their reflectivity on multilayer blanks, aerial
image on wafer plane and printed CDs depending on absorber thicknesses were simulated. This predicted an optimum
Ta-based absorber's thickness. Several patterned masks of LR-TaBN absorber with various thicknesses were prepared.
Each patterned mask was exposed with the newly developed small-field-exposure-tool (SFET). It was demonstrated
that optimized absorber thickness can, without loss of printability performance, reduce CD difference between
horizontal and vertical pattern that has been known to be caused by shadowing effect.
In this paper we focus exclusively on hole process. The motivation here is to investigate on the
performance of EUVL for hole patterning in relation to contributions from mask, exposure tool, and resist
process. For this purpose we use a waveguide simulation package that is capable of computing 3-D mask
structure at very fast speed. We investigated the patterning characteristics of arrayed holes influenced by mask
structure that involve absorber thickness and sidewall angle. Regarding the absorber thickness, we found in
our preliminary process window evaluation that thinner absorber mask requires lower dose than thick absorber
mask does. As lowering of dose is important for the development of cost effective EUVL technology, we have
intensively investigated impacts of thin mask on printability. As it turned out that thin absorber mask
evaluated in this paper required not only reduced dose but also exhibited improved process window. At the
same time we confirmed that top CD of mask pattern is sensitive to required dose even though bottom
reflection area of hole pattern happen to remain constant. The contributing parameters in shaping the side wall
are top CD, bottom CD, and thickness of the absorber. In this paper we studied the combined behavior of these
parameters that we call 3-D mask error impact. In Selete infrastructure, the technologies of EUVL for
realizing full field exposure system are developed using a small field exposure tool (SFET). Using this tool,
experimental hole formation was carried out. We also introduce simulations based on experiments.
One of the key issues in extreme ultraviolet lithography (EUVL) is the influence of defects on a mask because of the
high printing resolution of EUVL. In order to address this issue, it is necessary to estimate the critical size of an absorber
pattern defect and that of a repaired defect. The repair of an opaque defect by milling or of a clear defect by deposition
might not be perfect; so the area, height, and optical constant of the repair material must be taken into consideration. By
estimating the threshold of calculated aerial images, the critical dimension (CD) that can be printed was found to equal
the square root of the defect area. For the repair of opaque defects, residual Ta was found to be more likely to cause poor
printing than the etching of the multilayer by excessive milling. Since a clear defect is repaired with Ta with the same
optical properties as the absorber material, the CD error in printing is mainly caused by the repair of a CD error and is
not caused by an error in height that is less than ±25% of the height of the Ta absorber. The optimal optical constant of
the repair material was estimated by varying the refraction coefficient from 0.9199 to 0.9999 and the extinction
coefficient form 0.0001 to -0.0451. We found that carbon is a useful repair material that provides a CD error of at most
±0.5 nm around a defect with an area of 64 nm because the maximum refraction should be below 0.97.
In this paper we focus exclusively on hole process. The motivation here is to investigate on the performance of
EUVL for hole patterning in relation to contributions from mask, exposure tool, and resist process. In this paper we
investigated the patterning characteristics of arrayed, staggered, and isolated holes including features showing trench
The development of defect-free mask blanks including inspection is one of challenges for the implementation of
extreme ultraviolet lithography (EUVL). Among others, inspection of multilayer coated mask blanks with no oversight
of critical defects is a challenging issue for providing mask blanks with free defects.
In this paper, the printability of a small defect located underneath the reflective multilayer is studied, and the possibility
of inspection of the defect is investigated using MIRAI proof-of concept (POC) actinic inspection tool with a 26x
Schwarzschild optics of numerical aperture (NA) of 0.2. A critical defect giving a troublesome CD change can be detected. And the through focus characteristics in various shape defects are also analyzed.
Key issues of x-ray mask fabrication are EB mask writer and writing process on thin membrane. This paper shows precise x-ray mask writing technology using 100-kV EB writer on x- ray membrane mask. After several improvements of writing process including non-deformation mask holding and precise temperature control, absolute image placement accuracy within 10nm was obtained for giga-bit level ULSI pattern. Also the delineation characteristics of membrane mask writing using high-energy electron-beam including proximity effect and fogging effect were evaluated. Then accurate critical dimension control within 8 nm was achieved for such high density ULSI patterns. These good results satisfied the mask precision requirements for 100-nm node generation and below. So we fabricated precise x-ray masks having fine patterns of sub 100-nm node device for evaluation of advanced x-ray stepper.
Most important issues in a precise X-ray mask fabrication are the mask materials and EB writing to achieve good accuracy in critical dimension (CD) control and image placement (IP). However, 1-to-1 X-ray mask is required severe accuracy in comparison with photo reticles. The following discussions focus on how to realize the precise IP accuracy. We installed and evaluated 100-kV electron-beam (EB) mask writer (EB-X3), and developed the writing process on a thin membrane. Key factors in accurate EB mask writing include not only EB positioning accuracy but also mask distortions caused by mask holding and the temperature change of the mask and a mask holder. This paper presents mask distortion characteristics due to the holding, temperature change, and then, good results of mask accuracy of 4-Gb dynamic random access memory (DRAM) test patterns (gate and contact layers) and 90 nm SRAM test patterns. In addition, we employed the advanced PAT method with 4-multi-pass writing that adequately compensates the process-induced mask distortion and the beam drift. These improvements resulted in IP accuracy of better than 10 nm (3(sigma) ), 100 nm CD uniformity within 8 nm (mean shift +/- 3(sigma) ) and the overlay accuracy within 10 nm for 4-Gb gate and contact layers with a 24 mm x 24 mm area on the X-ray membrane mask. These results demonstrate that we can actually fabricate precise X-ray membrane masks that meet our final target of IP accuracy corresponding to the 100 nm technology node.
The keys to precision x-ray mask fabrication are the EB mask writer and the process of writing on a thin membrane. This paper concerns the delineation performance for 100 kV EB writing on x-ray membrane mask. We installed and evaluated an advanced EB mask writer, the EB-X3, which features an accelerating voltage of 100 kV and a 5-axes laser interferometer stage employing a laser measurement system with a resolution of 0.6 nm for high resolution and accuracy. The stable 100 kV EB has a good resolution around 50 nm and a beam address of 1 nm, which provide a repeatability of mark detection within 4 nm. As a result, an absolute image placement accuracy within 15 nm was obtained for 1G-bit level ULSI patterns. In addition, the combination of 100 kV EB and membrane process was found to reduce proximity effects. By several improvements including higher-order height correction and membrane process refinement, the final target of an absolute image placement error within 10 nm and a CD accuracy within 8 nm should be achieved in FY2000.
This article presents the alignment performance of the two- wavelength optical heterodyne alignment system in the x-ray stepper XS-1. The alignment accuracy obtained by the double- exposure method with a single mask and a Si trench wafer was better than 20 nm. The dependence of the alignment accuracy on Si trench depth indicated that the two wavelengths compliment each other and ensure a 3(sigma) of less than 20 nm. The alignment capabilities for other processed test wafers were also investigated by mix-and-match exposure. For etched SiO<SUB>2</SUB> and poly-Si film on a Si trench, an accuracy below 20 nm was obtained. For AlSiCu film sputtered on etched SiO<SUB>2</SUB>, there appeared systematic alignment offsets depended on die position, which are thought to be due to a wafer-induced shift. The systematic offset errors were eliminated by the use of send-ahead wafer and corrections for individual offsets on each die, and thus the alignment accuracy was improved to 20-40 nm for each alignment axis. The two-wavelength heterodyne alignment system of the XS-1 has sufficient potential for 130-nm lithography and below.
An opaque film coating and an anti-reflection (AR) film coating of x-ray masks are essential in order to get a higher alignment accuracy in optical heterodyne alignment systems. Not only the optical characteristics of the films, but also the stress and the durability in cleaning processes are important issues for the films. We investigated various materials from the viewpoints of the refractive index-matching with SiC, stress controllability and stability to a strong acid, an we have developed a material suitable for use with a Ta/SiC x-ray mask. We found that a sputtered Zr and Si compound oxide film fulfills the requirements of the AR film. We also found that a sputtered Ta film can be used as the opaque film, and we enhanced the diffraction efficiency of a mask mark by coating the AR film before coating the Ta opaque film on the mask mark.
This paper describes the results of a study to investigate the applicability of silicon carbide (SiC) x-ray masks to an optical-heterodyne alignment technique. SiC was deposited at a thickness of 2 micrometer on a 4 inch silicon (Si) wafer. Its surface roughness was improved from 15 nm Ra (geometrical average) to 0.2 nm Ra using a polishing method. Using this SiC material, x-ray masks with Ta absorber patterns for alignment marks and overlay measurement were fabricated. To obtain a high overlay repeatability, we have deposited an anti- reflection coating (ARC) on both sides of the x-ray mask, which increased an optical transmission at a wavelength of 785 nm from 37% to 73%. We have also deposited an opaque coating (OPC) on the mask alignment mark. Using the x-ray mask, the overlay repeatability by mix-and-match method was evaluated. The overlay repeatability near the X, Y and (theta) alignment marks was 21 nm, 21 nm, and 49 nm (3 sigma) for the corresponding axes. The overlay repeatability of the X and Y directions was 61 nm and 54 nm (3 sigma) in a wafer. These results are equivalent to the results obtained using SiN x-ray masks. From these results, we consider that SiC x-ray masks are applicable to optical heterodyne alignment, and can also be used in practical x-ray lithography.