As the design node of memory device shrinks, OPC model accuracy is becoming ever more critical from development to manufacturing. To improve the model accuracy, more and more physical effects are analyzed and terms for those physical effects are added. But it is unachievable to capture the complete physical effects. In this study, deep neural network is employed and studied to improve model accuracy. Regularization is achieved using physical guidance model. To address overfitting issue, high volume of contour based edge placement (EP) gauges (>10K) are generated using fast eBeam tool (eP5) and metrology processing software (MXP) without increasing turnaround time. It is shown that the new approach improved model accuracy by >47% compared to traditional approach on >1.4K verification gauges.
As the DRAM node shrinks down to its natural limit, photo lithography is encountering many difficulties.
3Xnm DRAM node seems to be the limit for ArF Immersion. Until the arrival of EUV, double patterning (DPT) or
spacer double patterning (SPT) seems like the next solution. But the problem with DPT or SPT is that both increases
process step their by increasing the final costs of the device. So limiting the use of DPT or SPT is very important for
device fabrication. For 3Xnm DRAM, storage node is one of the candidates to eliminate DPT or SPT process. But this
method may cost lower process margin and degradation of pattern image. So, solution to these problems is very crucial.
In this study, we will realize storage node (SN) pattern for 3Xnm DRAM node with improved process margin. First we
will discuss selection of illumination for optimal condition second, correction of the mask will be introduced. We will
also talk about the usage of various RET such as model based assist feature. Value such as DOF, EL and CDU (critical
dimension uniformity) will be evaluated and analyzed.