Corner rounding improvement is critical to device performance, yield, and cell area reduction. In this paper, we present a method to use dual tone sub-resolution assist feature (SRAF) to improve both the outer corner rounding and inner corner rounding to improve the pattern quality. The simulation data and wafer data are presented. A few parameters have been investigated, such as the position of the SRAF, the shape of the SRAF, resist type and mask tone. The preliminary results show that more than 40% reduction of both inner corner rounding and outer corner rounding can be achieved by placing sub-resolution assist features at appropriate locations. The limit of corner rounding improvement is determined by mask rule check (MRC) and resist sensitivity. As a conclusion, a general methodology for dual tone SRAF placement for corner rounding improvement is suggested.
Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device.
Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing. Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP. We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.
Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.