For digital imagery, face detection and identification are functions of great importance in wide-ranging applications, including full facial recognition systems. The development and evaluation of unique and existing face detection and face identification applications require a significant amount of data. Increased availability of such data volumes could benefit the formulation and advancement of many biometric algorithms. Here, the utility of using synthetically generated face data to evaluate facial biometry methodologies to a precision that would be unrealistic for a parametrically uncontrolled dataset, is demonstrated. Particular attention is given to similarity metrics, symmetry within and between recognition algorithms, discriminatory power and optimality of pan and/or tilt in reference images or libraries, susceptibilities to variations, identification confidence, meaningful identification mislabelings, sensitivity, specificity, and threshold values. The face identification results, in particular, could be generalized to address shortcomings in various applications and help to inform the design of future strategies.
An efficient parallel architecture design for the iris unwrapping process in a real-time iris recognition system using the
Bresenham Circle Algorithm is presented in this paper. Based on the characteristics of the model parameters this
algorithm was chosen over the widely used polar conversion technique as the iris unwrapping model. The architecture
design is parallelized to increase the throughput of the system and is suitable for processing an inputted image size of
320 × 240 pixels in real-time using Field Programmable Gate Array (FPGA) technology. Quartus software is used to
implement, verify, and analyze the design’s performance using the VHSIC Hardware Description Language. The
system’s predicted processing time is faster than the modern iris unwrapping technique used today∗.
Commercially available hardware, freely available algorithms, and authors’ developed software are synergized successfully to detect and recognize subjects in an environment without visible light. This project integrates three major components: an illumination device operating in near infrared (NIR) spectrum, a NIR capable camera and a software algorithm capable of performing image manipulation, facial detection and recognition. Focusing our efforts in the near infrared spectrum allows the low budget system to operate covertly while still allowing for accurate face recognition. In doing so a valuable function has been developed which presents potential benefits in future civilian and military security and surveillance operations.
Improvements in face detection performance would benefit many applications. The OpenCV library implements a standard solution, the Viola-Jones detector, with a statistically boosted rejection cascade of binary classifiers. Empirical evidence has shown that Viola-Jones underdetects in some instances. This research shows that a truncated cascade augmented by a neural network could recover these undetected faces. A hybrid framework is constructed, with a truncated Viola-Jones cascade followed by an artificial neural network, used to refine the face decision. Optimally, a truncation stage that captured all faces and allowed the neural network to remove the false alarms is selected. A feedforward backpropagation network with one hidden layer is trained to discriminate faces based upon the thresholding (detection) values of intermediate stages of the full rejection cascade. A clustering algorithm is used as a precursor to the neural network, to group significant overlappings. Evaluated on the CMU/VASC Image Database, comparison with an unmodified OpenCV approach shows: (1) a 37% increase in detection rates if constrained by the requirement of no increase in false alarms, (2) a 48% increase in detection rates if some additional false alarms are tolerated, and (3) an 82% reduction in false alarms with no reduction in detection rates. These results demonstrate improved face detection and could address the need for such improvement in various applications.
Proc. SPIE. 8063, Mobile Multimedia/Image Processing, Security, and Applications 2011
KEYWORDS: Digital signal processing, Image processing, Video, Field programmable gate arrays, Parallel processing, Video surveillance, Video processing, Embedded systems, Prototyping, Standards development
FPGA devices with embedded DSP and memory blocks, and high-speed interfaces are ideal for real-time video
processing applications. In this work, a hardware-software co-design approach is proposed to effectively utilize FPGA
features for a prototype of an automated video surveillance system. Time-critical steps of the video surveillance
algorithm are designed and implemented in the FPGAs logic elements to maximize parallel processing. Other non timecritical
tasks are achieved by executing a high level language program on an embedded Nios-II processor. Pre-tested and
verified video and interface functions from a standard video framework are utilized to significantly reduce development
and verification time. Custom and parallel processing modules are integrated into the video processing chain by Altera's
Avalon Streaming video protocol. Other data control interfaces are achieved by connecting hardware controllers to a
Nios-II processor using Altera's Avalon Memory Mapped protocol.
Iris recognition algorithms depend on image processing techniques for proper segmentation of the iris. In the Ridge
Energy Direction (RED) iris recognition algorithm, the initial step in the segmentation process searches for the pupil by
thresholding and using binary morphology functions to rectify artifacts obfuscating the pupil. These functions take
substantial processing time in software on the order of a few hundred million operations. Alternatively, a hardware
version of the binary morphology functions is implemented to assist in the segmentation process. The hardware binary
morphology functions have negligible hardware footprint and power consumption while achieving speed up of 200 times
compared to the original software functions.
Proc. SPIE. 7351, Mobile Multimedia/Image Processing, Security, and Applications 2009
KEYWORDS: Digital signal processing, Facial recognition systems, Statistical analysis, Detection and tracking algorithms, Sensors, Image processing, Video, Field programmable gate arrays, Computer simulations, Video surveillance
The first step in a facial recognition system is to find and extract human faces in a static image or video frame. Most face
detection methods are based on statistical models that can be trained and then used to classify faces. These methods are
effective but the main drawback is speed because a massive number of sub-windows at different image scales are
considered in the detection procedure. A robust face detection technique based on an encoded image known as an
"integral image" has been proposed by Viola and Jones. The use of an integral image helps to reduce the number of
operations to access a sub-image to a relatively small and fixed number. Additional speedup is achieved by incorporating
a cascade of simple classifiers to quickly eliminate non-face sub-windows. Even with the reduced number of accesses to
image data to extract features in Viola-Jones algorithm, the number of memory accesses is still too high to support realtime
operations for high resolution images or video frames. The proposed hardware design in this research work
employs a modular approach to represent the "integral image" for this memory-intensive application. An efficient
memory manage strategy is also proposed to aggressively utilize embedded memory modules to reduce interaction with
external memory chips. The proposed design is targeted for a low-cost FPGA prototype board for a cost-effective face