In this paper, we will discuss patterning challenges of EUV lithography to apply 1xnm node DRAM. EUV lithography is
positioned on essential stage because development stage for DRAM is going down sub-20nm technology node. It is time to decide how to make sub-20nm node DRAM. It will be the simplest and cost effective way to make device with
matured EUVL. But in spite of world-wide effort to develop EUV lithography, the maturity of EUV technology is still
lower than conventional ArF immersion lithography. So, DRAM manufacturers are considering several candidates such
as DSA, DPT and MPT simultaneously. In addition, DRAM manufacturers are considering new cell layout and new
memory also. For this study, we investigate process window and shadow effect across exposure field of sub-20nm node DRAM cell. We also performed an overlay matching experiment between 0.25NA EUV scanner and 1.35NA ArF
immersion scanner. In addition, we will compare EUV lithography with ArF immersion DPT or SPT in view of patterning performance. Finally, we will discuss some technical issues to applying EUV lithography such as flare, resist LER, EUV OPC and illumination condition using 0.25NA EUV scanner.
In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant
progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the
development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution
limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for
developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as
complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization)
process have also applied as design rule is decreased, the improvement of process overlay control is very important.
In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual
experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with
comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the
process effects such as hard mask material, thermal process and CMP process that affect to overlay control.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In this paper, we will present experimental results on sub-40nm node patterning of DRAM and some technical issues for capping freezing in simplified double patterning lithography. Lithography resolution limit of single pattern is 40nm in ArF immersion process. For sub-40nm patterning, we have to use double patterning lithography or EUV process. But, double patterning lithography process is very complicated and expensive solution. And EUV volume production technology will be not ready until 2012. Therefore, we have tried a simplified double patterning lithography.
ArF Immersion lithography is expected to be a production-worthy technology for sub-60nm DRAM. It gives wider
process window and better CD uniformity at the cost of defects and overlay accuracy. It is generally mentioned that
immersion defects are generated during exposure and removed through pre-soak and post-soak process. A lot of efforts
are being made towards less defect generation during exposure and more defect removal through pre-soak and postsoak
We have experienced a variety of immersion defects and classified them into four types: bubble defect, water mark
defect (T-top & Stain), swelling defect and bridge defect (Macro & Micro). We have worked very hard to reduce each
immersion defects with immersion exposure and system. In this paper, we investigate method to reduce each
immersion defects: bubble, water mark, swelling and bridge through our experiment.
Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.