Proc. SPIE. 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014)
KEYWORDS: Digital signal processing, Logic, Clocks, Laser range finders, Data storage, Telecommunications, Signal processing, Orthogonal frequency division multiplexing, Computer architecture, Standards development
This paper presents a high-throughput and reconfigurable processor for fast Fourier transformation (FFT) processing based on SDR methodology. It adopts application specific instruction-set (ASIP) and single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. Moreover, a novel 3-dimension multi-bank memory is proposed for parallel conflict-free accesses. The overall throughput and power-efficiency are greatly enhanced by parallel and streamline processing. A test chip supporting 64~2048-point FFT is setup for experiment. Logic synthesis reveals a maximum clock frequency of 500MHz and an area of 0.49 mm<sup>2</sup> for the processor's logic using a low power 45-nm technology, and the dynamic power estimation is about 96.6mW. Compared with previous works, our FFT ASIP achieves a higher energy-efficiency with relative low area cost.
Proc. SPIE. 8784, Fifth International Conference on Machine Vision (ICMV 2012): Algorithms, Pattern Recognition, and Basic Technologies
KEYWORDS: Digital signal processing, Data modeling, Digital filtering, Data processing, Signal processing, Nanoimprint lithography, Wireless communications, Data communications, Matrix multiplication, Standards development
With the development of international wireless communication standards, there is an increase in computational
requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new
processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital
signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In
addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the
development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to
prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable
SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture
which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three
common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform.
Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the