Multi-patterning lithography for future technology nodes in logic and memory are driving the allowed on-product overlay error in an DUV and EUV matched machine operation down to values of 2 nm and below. The ASML ORION alignment sensor provides an effective way to deal with process impact on alignment marks. In addition, optimized higher order wafer alignment models combined with overlay metrology based feedforward correction schemes are deployed to control the process induced overlay variability from wafer-to-wafer and lot-to-lot. In addition machine learning based algorithms based on hybrid metrology inputs, strengthen the control capabilities for high volume manufacturing. The increase of the number of process layers in semiconductor devices results in an increase of control complexity of the total overlay and alignment control strategy. This complexity requires a holistic solution approach, that addresses total overlay optimization from process design, to process setup, and process control in high volume manufacturing. We find the optimum combination between feedforward and feedback, by having feedback deal with constant and predictable parts of overlay and have scanner wafer alignment covering the wafer-to-wafer variable part of overlay. In this paper we present investigation results using more wavelengths for wafer alignment and show the benefits in wavelength selection and recipe optimization. We investigate the wafer-to-wafer variable content of two experiment cases and show that a sample scheme of about 60 marks is well capable estimating the model parameters describing the grid. Finally, we show initial results of using level sensor metrology data as hybrid input to the derivation of the exposure grid.
Three methods to minimize the impact of alignment mark asymmetry on overlay variation are demonstrated. These methods are measurement based optimal color weighting (OCW), simulation based optimal color weighting, and wafer alignment model mapping (WAMM). Combination of WAMM and OCW methods delivers the highest reduction in overlay variation of 1.3nm (X direction) and 1.2nm (Y direction) as compared to best single color recipe. Simulation based OCW produces a similar reduction in overlay variation as compared to measurement based OCW, and simulation based OCW has the advantage that the scanner alignment recipe with optimize weights can be determined before the mark asymmetry excursion has occurred. Finally, WAMM is capable of reducing the contribution of mark asymmetry on overlay by using a more optimal high order wafer alignment recipe. Capabilities of WAMM can also be combined with OCW solutions.
Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.
In this paper we discuss edge placement error (EPE) for multi-patterning application and compare the EPE budget with the one for EUV single expose application case. These two patterning methods are candidate for the manufacturing of 10-nm and 7-nm logic semiconductor devices. EUV will enable 2D random pattern layout, while in the multi-patterning case a more restricted 1D design layout is needed. For the 1D design approach we discuss the patterning control spacer pitch division resulting in complex multi-layer alignment and EPE optimization strategies. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets. We use 10-nm node experimental data and extrapolate the error budgets towards the 7-nm technology node. The experimental data will be based on NXE:3300B and NXT:1960Bi/NXT:1970Ci exposure systems. The results are compared to the more straightforward alternative of using single expose patterning with EUV for all critical layers.
As leading edge lithography moves to 22-nm design rules, low k1 technologies like double patterning are the new
resolution enablers, and system control and setup are the new drivers to meet remarkably tight process requirements. The
way of thinking and executing setup and control of lithography scanners is changing in four ways.
First, unusually tight process tolerances call for very dense sampling , which in effect means measurements at high
throughput combined with high order modeling and corrections to compensate for wafer spatial fingerprint.
Second, complex interactions between scanner and process no longer allow separation of error sources through
traditional metrology approaches, which are based on using one set of metrology tools and methods for setup and
another for scanner performance control. Moreover, setup and control of overlay is done independently from CD
uniformity, which in effect leads to independent and conflicting adjustments for the scanner.
Third, traditional CD setup and control is based on the focus and dose calculated from their CD response and not from
measurement of their effect on pattern profile, which allows a clean and orthogonal de-convolution of focus and dose
variations across the wafer.
Fourth, scanner setup and control has to take into consideration the final goal of lithography, which is the accurate
printing of a complex pattern describing a real device layout. To this end we introduce a new setup and control
metrology step: measuring-to-match scanner 1D and 2D proximity.
In this paper we will describe the strategy for setup and control of overlay, focus, CD and proximity based on the
YieldStarTM metrology tool and present the resulting performance. YieldStar-200 is a new, high throughput metrology
tool based on a high numerical aperture scatterometer concept. The tool can be used stand-alone as well as integrated in a
processing track. It is suitable for determining process offsets in X,Y and Z directions through Overlay and Focus
measurements respectively. In addition CD profile information can be measured enabling proximity matching
By using a technique  to de-convolve dose and focus based on the profile measurement of a well-characterized
process monitor target, we show that the dose and focus signature of a high NA 193nm immersion scanner can be
effectively measured and corrected. A similar approach was also taken to address overlay errors using the diffraction
based overlay capability  of the same metrology tool. We demonstrate the advantage of having a single metrology tool
solution, which enables us to reduce dose, focus and overlay variability to their minimum non-correctable signatures.
This technique makes use of the high accuracy and repeatability of the YieldStar tool and provides a common reference
of scanner setup and user process. Using ASML's YieldStar in combination with ASML scanners, and control solutions
allows for a direct link from the metrology tool to the system settings, ensuring that the appropriate system settings can
be easily and directly updated.
FlexRay programmable illumination and LithoTuner software is combined in several use cases. The first use case is
optical proximity error (OPE) minimization. Simulation predicts the rms OPE error is reduced by 39% with LithoTuner
and FlexRay, and is confirmed via experiment with a reduction of 33%. For minimizing the OPE error, two types of
illumination tuning was performed, sigma tuning and freeform tuning. The sigma tuning is able to reduce the mean-totarget
critical dimension (CD) error, but the CD error variance is unaffected. Freeform tuning, however, is able to reduce
both the mean-to-target CD and the CD error variance. The second use case is matching two ArF scanners, a XT:1950Hi
with FlexRay to a XT:1700Fi with diffractive optical element (DOE) illumination. With LithoTuner and FlexRay,
simulation predicts the CD error post-matching is reduced by 51%, and experiment was able to achieve a reduction of
Holistic lithography is needed to cope with decreasing process windows and is built on three pillars: Scanner Tuning,
Computational Lithography and Metrology & Control. The relative importance of stability to the overall manufacturing
process latitude increases. Overlay and focus stability control applications are important elements in improving stability
of the lithographic process. The control applications rely on advanced control algorithms and fast and precise metrology.
To address the metrology needs at the 32 nm node and beyond, an optical scatterometry tool was developed capable of
measuring CD, focus-dose as well as overlay. Besides stability and control of lithographic performance also scanner
matching is a critical enabler where application development and metrology performance are key. In this paper we
discuss the design and performance of the metrology tool, the focus and overlay control application and the application
of scatterometry in scanner matching solutions.
The fingerprint of the optical proximity effect, OPE, is required to develop each process node's optical proximity
correction (OPC) model. This model should work equally well on different exposure systems. However, small
differences in optical and mechanical properties in the lithographic system can lead to a different CD characteristic for a
given OPC. It becomes beneficial to match the OPE of one scanner to the scanner population in a fab. Here, we focus on
aspects of angle resolving scatterometry metrology used for OPE matching of two XT:1700i scanners and compare those
to SEM metrology. The capability of the scatterometry tool for monitoring the stability of OPE is evaluated.
Scatterometry allows measuring the side wall angle, SWA, of a resist profile and this can be used as a measure for focus.
Here, focus comparison by SWA is included into the matching process. For the application used here, the residual RMS
mismatch through pitch for scatterometry could be reduced to 0.2nm compared to 0.5nm for CD-SEM.
In this paper we present a methodology to investigate and optimize the CD balance between the four
features of a final 32nm lines and space pattern created by spacer pitch doubling.
Metrology (SEM and scatterometry) was optimized to measure and separate the two lines and the
two spaces of the 32nm features. In case a space unbalance emerged during the various processing
steps such as etch and deposition, this was compensated by calculating and feed-back local dose
offsets to the scanner. For the spacer process used in this study we observe 20..40% improvement in
space CDU and space balance, when applying the dose corrections.
Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have
equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to
process control, metrology and integration, but seem feasible for the 32nm node.
In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double
patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific
aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and
spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD
populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple
populations in order to meet comparable 10% CDU as in single exposure.
We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming
capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After
compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and
multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU
populations entangled overlay into CDU.
Semiconductor industry has an increasing demand for improvement of the total lithographic overlay performance. To
improve the level of on-product overlay control the number of alignment measurements increases. Since more mask
levels will be integrated, more alignment marks need to be printed when using direct-alignment (also called layer-to-layer
alignment). Accordingly, the alignment mark size needs to become smaller, to fit all marks into the scribelane. For
an in-direct alignment scheme, e.g. a scheme that aligns to another layer than the layer to which overlay is being
measured, the number of needed alignment marks can be reduced.
Simultaneously there is a requirement to reduce the size of alignment mark sub-segmentations without compromising the
alignment and overlay performance. Smaller features within alignment marks can prevent processing issues like erosion,
dishing and contamination. However, when the sub-segmentation size within an alignment mark becomes comparable to
the critical dimension, and thus smaller than the alignment-illuminating wavelength, polarization effects might start to
occur. Polarization effects are a challenge for optical alignment systems to maintain mark detectability. Nevertheless,
this paper shows how to actually utilize those effects in order to obtain enhanced alignment and overlay performance to
support future technology nodes.
Finally, another challenge to be met for new semiconductor product technologies is the ability to align through semi-opaque
materials, like for instance new hard-mask materials. Enhancement of alignment signal strength can be reached
by adapting to new alignment marks that generate a higher alignment signal. This paper provides a description of an
integral alignment solution that meets with these emerging customer application requirements. Complying with these
requirements will significantly enhance the flexibility in production strategies while maintaining or improving the
alignment and overlay performance. This paper describes the methodology for optimization of the alignment strategy.
In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor , improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented. In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.
After the introduction of the ATHENATM alignment sensor, advanced applications of the sensor data are becoming increasingly important to meet the tightening overlay specifications for future technology nodes. As part of the total overlay budget, the effects of different alignment strategies on overlay performance need to be investigated. Keeping in mind that such strategies are simple and easy to use, two developments are addressed in this paper: advanced alignment recipes and advanced mark designs. An alignment recipe defines which signals from the sensor are used to calculate the aligned position. By making advanced use of the available data, wafer alignment can be made more accurate and more robust to processing effects. It is shown that the new Smooth Color Dynamic alignment recipes exhibit good overlay performance on STI, Cu dual damascene and W-CMP / Al-PVD layers. Since Smooth Color Dynamic also takes away the choice of a particular color in the alignment recipe, it is the preferred alignment recipe for all product layers. The optimum design of an alignment mark depends on the process characteristics. As the process characteristics may vary over time, the optimum mark design can change accordingly. To cover a larger process range, multiple alignment mark designs are combined in a new multi-grating mark: the Versatile Scribeline Primary Mark (VSPM). By measuring all gratings during regular production, the optimum grating of a VSPM can be selected and aligned with a Smooth Color Dynamic alignment recipe. For CMP layers a further overlay improvement can be achieved if all gratings have comparable phase depths. By combining alignment signals from different gratings in a predictive alignment recipe, wafer-to-wafer variations due to CMP effects can be reduced.
In a joint development program between ASML and Motorola a new set of alignment marks have been designed and tested using the ATHENA off-axis alignment system on the ASML scanner. The new marks were analyzed for improved robustness against varying wafer-processing conditions to verify improved overlay capability and stability. These new marks have been evaluated on a set of dual inlaid-copper short flow wafers, with layer stacks consisting of 180 nm technology generation dielectric materials. Typical process variation has been deliberately introduced as part of the designed experiment to study the performance robustness of the new alignment marks. This paper discusses the new mark design and the theoretical reasons for mark design and/or integration change. Results shown in this paper provide initial feedback as to the viability of new variations of ATHENA alignment marks, specifically the SSPM and VSPM. Included in the results is the investigation to further stabilization of alignment signal strength. New ideas that are currently under development, to increase alignment mark signal strength stability, are discussed.
The continuing reduction of IC device dimensions puts stringent demands on the corresponding overlay performance. As part of the total overlay budget, the effects of the different process parameters need to be characterized and well understood. In a joint development program between IMEC and ASML, the robustness of different alignment strategies to process parameters has been evaluated using the ATHENA alignment system. This paper looks at both Front-end (Shallow Trench Isolation) and Back-end (W-CMP and copper dual damascene) processing. To investigate the effect of STI processing on alignment marks in Front-end processing an extensive evaluation has been performed in which both mark design and process parameters have been varied. The robustness to typical long term process variation at the STI CMP step in a production environment has also been evaluated. To improve the robustness of alignment marks in Back-end processing, new mark designs have been evaluated. These designs have been evaluated for two different processes. The first uses traditional W-CMP and sputtered aluminum. The second uses copper dual damascene, with layer stacks consisting of both conventional and low-k dielectric materials. This knowledge will be used to generate alignment strategies for future technology nodes.
Advances in wafer processing techniques and the increase of wafer size to 300 mm present new challenges to overlay performance. This paper focuses on advances n the area of process-induced alignment accuracy using the ASML ATHENA alignment system. In the experiments, process variations were deliberately increased to characterize the influence of process-tool settings on wafer alignment performance. In the STI process flow, overlays of <32 nm on marks in silicon or marks in the STI layer have been achieved. In the back-end-of-line, aluminum layers exhibit a significant shift of alignment marks and off-line metrology targets. A geometrical model of the sputter tool is used to explain the origin of this effect. Possible improvements in process corrections are indicated. For the copper dual damascene process investigated here, the dielectrics are non-absorbing. Overlays of 25 nm on marks in silicon and 29 nm on marks in the metal layer are obtained. On 300 mm wafers, a new measurement method is capable of measuring process effects to an accuracy within 6.2 (3(sigma) ). This method is used to measure resist spin effects.
To guarantee less than 45 nm product overlay required for the 130 nm IC technology node a key in lithographic tools is a sophisticated wafer alignment sensor that is able to deal with the influences of new, advanced IC processing. To prove that product overlay performance in this range is achievable, overlay results are presented that confirm the operational concept of the new ATHENA alignment sensor on various advanced processes in both front-end as well as back-end-of-line. In particular, the influences related to Chemical Mechanical Polishing (CMP) have been studied. The robustness of the system to large variations of W-CMP process parameters is highlighted. It is argued that full exploitation of the flexibility of the sensor will allow further optimization of its operation in actual production environments and that a product overlay of 35 nm is feasible.
Processes such as chemical mechanical polishing and spin coating can result in the asymmetric deformation of alignment marks. In this paper, the effects of such asymmetric mark deformations on the accuracy of the stepper alignment system are investigate. An advanced phase grating alignment system is presented which is more robust against the above mentioned process-induced alignment deviations. The potential of the new alignment system will be illustrated with result of both numerical simulations and experimental measurements. Various process modules that are known to cause mark deformations have been investigated.
A new latent image metrology technique is discussed that determines best focus with a precision of (sigma) equals 20 nm. This technique uses the existing alignment system of an ASM-L wafer stepper and requires no hardware or software modifications. The user just needs a standard chrome reticle. It can operate for machine setup at the factory, but also in-process for fully automatic self calibration of focus and tilt. A typical measurement takes a few minutes.