Below the 28nm node the difficulty of using subresolution assist features (SrAFs) in OPC/RET schemes increases substantially with each new device node. This increase in difficulty is due to the need for tighter process window control for smaller target patterns, the increased risk of SrAF printing , and also the increased difficulty of SrAF mask manufacture and inspection. Therefore, there is a substantially increased risk of SrAFs which violate one or more manufacturability limits.
In this paper, we present results of our work to evaluate methods to pre-characterize designs which are likely to become problematic for SrAF placement. We do this by evaluating different machine learning methods, inputs and functions.
As technology advances into deep submicron nodes, the mask manufacturing process accuracy become more
important. Mask Process Correction (MPC) has been transitioning from Rules-Based Mask Process correction to
Model-Based Mask Process Correction mode. MPC is a subsequent step to OPC, where additional perturbation is
applied to the mask shapes to correct for the mask manufacturing process. Shifting towards full model-based MPC is
driven mainly by the accuracy requirements in advanced technology nodes, both for DUV and EUV processes.
In the current state-of-the-art MPC process, MPC is completely decoupled from OPC, where each of them assumes
that the other is executing perfectly. However, this decoupling is not suitable anymore due to the limited tolerance in
the mask CDU budget and the increased wafer CDU requirements required from OPC. It is becoming more
important to reduce any systematic mask errors, especially where they matter the most.
In this work, we present a new combined-verification methodology that allows testing the combined effect of mask
process and lithography process together and judging the final wafer patterning quality. This has the potential to
intercept risks due to superposition of OPC and MPC correction residual errors, and capturing and correcting such a
previously hidden source of patterning degradation.
MEEF, or Mask Error Enhancement Factor, is simply defined as the ratio of the change in printed wafer
feature width to the change in mask feature width scaled to wafer level. It is important in chip
manufacturing that leads to the amplification of mask errors, creating challenges with both achieving
dimensional control tolerances and ensuring defect free masks, as measured by on-wafer image quality. As
lithographic imaging continues to be stressed, using lower and lower k1 factor resolution enhancement
techniques, the high MEEF areas present on advanced optical masks creates an environment where the
need for increased mask defect sensitivity in high-MEEF areas becomes more and more critical.
There are multiple approaches to mask inspection that may or may not provide enough sensitivity to detect
all wafer-printable defects; the challenge in the application of these techniques is simultaneously
maintaining an acceptable level of mask inspectability. The higher the MEEF, the harder the challenge will
be to achieve and appropriate level of sensitivity while maintaining inspectability…and to do so on the
geometries that matter.
The predominant photomask fabrication inspection approach in use today compares the features on the
reticle directly with the design database using high-NA optics. This approach has the ability to detect small
defects, however, when inspecting aggressive OPC, it can lead to the over-detection of inconsequential, or
nuisance defects. To minimize these nuisance detections, changing the sensitivity of the inspection can
improve the inspectability of a mask inspected in high-NA mode, however, it leads to the inability to detect
subtle, yet wafer-printable defects in High-MEEF geometry, due to the fact that this ‘desense’ must be
applied globally. There are also ‘lithography-emulating’ approaches to inspection that use various means to
provide high defect sensitivity and the ability to tolerate inconsequential, non-printing defects by using
scanner-like conditions to determine which defects are wafer printable. This inspection technique is
commonly referred to as being ‘lithography plane’ or ‘litho plane,’ since it’s assessing the mask quality
based on how the mask appears to the imaging optics during use, as proposed to traditional ‘reticle plane’
inspection which is comparing the mask only with its target design.
Regardless of how the defects are detected, the real question is when should they be detected? For larger
technology nodes, defects are considered ‘statistical risks’…i.e., first they have to occur, and then they
have to fall in high-MEEF areas in order to be of concern, and be below the detection limits of traditional
reticle-plane inspection. In short, the ‘perfect storm’ has to happen in order to miss printable defects using
well-optimized traditional inspection approaches. The introduction of lithographic inspection techniques
has revealed this statistical game is a much higher risk than originally estimated, in that very subtle waferprintable
CD errors typically fall into the desense band for traditional reticle plane inspection. Because printability is largely influenced by MEEF, designs with high-MEEF values are at greater risk of traditional
inspection missing printable CD errors. The question is… how high is high… and at what MEEF is optical
inspection at the reticle plane sufficient? This paper will provide evaluation results for both reticle-plane
and litho-plane inspections as they pertain to varying degrees of MEEF. A newly designed high-MEEF
programmed defect test mask, named VAMPIRE, will be introduced. This test mask is based on 7 nm node
technology and contains intentionally varying degrees of MEEF as well as a variety of programmed defects
in high-MEEF environments…all of which have been verified for defect lithographic significance on a
Zeiss AIMS system.
To transfer an electronic circuit from design to silicon, a lot of stages are involved in between. As technology evolves, the design shapes are getting closer to each other. Since the wavelength of the lithography process didn't get any better than 193nm, optical interference is a problem that needs to be accounted for by using Optical Proximity Correction (OPC) algorithms. In earlier technologies, simple OPC was applied to the design based on spatial rules. This is not the situation in the recent technologies anymore, since more optical interference took place with the intensive scaling down of the designs. Model-based OPC is a better solution now to produce accurate results, but this comes at the cost of the increased run time. Electronic Design Automation (EDA) companies compete to offer tools that provide both accuracy and run time efficiency. In this paper, we show that optimum usage of some of these tools can ensure OPC accuracy with better run time. The hybrid technique of OPC uses the classic rule-based OPC in a modern fashion to consider the optical parameters, instead of the spatial metrics only. Combined with conventional model-based OPC, the whole flow shows better results in terms of accuracy and run time.