The Self-Aligned Quadruple Patterning (SAQP) process is one of the most suitable techniques for the patterning of under-20 nm half-pitch lines and spaces (L/S) patterns because it requires only one lithography step, resulting in a relatively low process cost. A serious problem when applying the SAQP process to real devices is the printability of defects in the photomask to the wafer because the effect of the mask defects may be enlarged when the defects are transferred to the spacer pattern. In this study, we evaluate the mask defect printability for both opaque and clear defects in the SAQP process in order to clarify the limit size of the defects on the photomask and to clarify whether the acceptable mask defect size given by ITRS was too small. The defect sizes of both the opaque and clear defects were relaxed as the wafer process progressed from lithography to SAQP. The acceptable mask defect size in the SAQP process found to be 70 nm, which is relaxed from that in ITRS2013.
Line pattern collapse attracts attention as a new problem of the L&S formation in sub-20nm H.P feature. Line pattern collapse that occurs in a slight non-uniformity of adjacent CD (Critical dimension) space using double patterning process has been studied with focus on micro-loading effect in Si etching. Bias RF pulsing plasma etching process using low duty cycle helped increase of selectivity Si to SiO<sub>2</sub>. In addition to the effect of Bias RF pulsing process, the thin mask obtained from improvement of selectivity has greatly suppressed micro-loading in Si etching. However it was found that micro-loading effect worsen again in sub-20nm space width. It has been confirmed that by using cycle etch process to remove deposition with CFx based etching micro-loading effect could be suppressed. Finally, Si etching process condition using combination of results above could provide finer line and space without "line pattern collapse" in sub-20nm.
We obtained the acceptable mask defect size for both opaque and clear defects in the spacer patterning process using the
fail-bit-map analysis and a mask with programmed defects. The spacer patterning process consists of the development of
photoresist film, the etching of the core film using the photoresist pattern as the etching mask, the deposition of a spacer
film on both sides of the core film pattern, and the removal of the core film. The pattern pitch of the spacer film becomes
half that of the photoresist. Both the opaque defect and the clear defect of the mask resulted in a short defect in the spacer
pattern. From the fail-bit-map analysis, the acceptable mask defect size for opaque and clear defects was found to be
80nm and 120nm, respectively, which could be relaxed from that in ITRS2008. The difference of the acceptable mask
defect size for opaque and clear defects comes from the difference of the defect printability at the resist development.
Novel optical proximity correction (OPC) and design for manufacturability (DfM) methodology for threedimensional
(3D) memory device is proposed to overcome emerging hotspot issues caused by larger process proximity
effect (PPE) due to unavoidable high-aspect patterning process. To realize robust pattern formation for lithography and
reactive-ion etching (RIE) processes, the following methodologies are introduced: i) OPC is carried out by using
averaged or designed optics not ideal to make robust pattern formation for optical variation of exposure tool, ii)
lithography compliance check (LCC) is done under the worst optical condition to detect hotspots induced by optical
variation of exposure tool, and modification of layout and OPC condition is performed to remove hotspots, iii) hotspots
induced by RIE process are checked by using etching simulation with empirical RIE model, and modification of layout,
PPC and OPC scheme is performed to remove hotspots. In this study, it is confirmed that our proposed novel OPC and
DfM methodology is promising for robust pattern formation in upcoming 3D memory device.
Turn around time (TAT) of mask qualification is one of the most important factors for high-end mask installation to
LSI production lines. Accurate mask qualification with shorter TAT for mask process updates brings about steep rampup
of LSI volume production. In this paper, an innovative approach is described for mask qualification with a die-todatabase
(D2DB) inspection system that can accomplish both qualification accuracy and short TAT in low k1
lithography. The D2DB inspection system, NGR2100, has features satisfying the above requirements owing to larger
field of view (FOV) and higher probe current than those of CD-SEM. Compared with the conventional optical inspection
tool, the system provided higher accuracy in extracting fatal defects called "hotspots". Also, hotspots extracted by the
system covered all killer hotspots extracted by electrical and physical analysis . The contours of hotspots extracted by
NGR2100 are transferred to GDS data format to compare hotspots between conventional mask process and updated
mask process. If the differences between the contours are within an assumed tolerance, the system provides the
qualification for updated mask process. As a result, qualification TAT was reduced by as much as two months compared
with the conventional electrical qualification on wafers.
We have constructed hotspot management flow with a die-to-database (D2DB) inspection system for spacer
patterning technologies (SPTs) which are among the strongest candidates in double patterning technologies below 3x nm
half-pitch generations. At SPIE 2006, we reported in "Hotspot management" that extracted hotspot by full-chip
lithography simulation could be quickly fed back to OPC, mask making, etc. Since the SPT includes process complexity
from resist patterning to final device patterning, however, it is difficult to exactly estimate hotspots on final patterned
features on wafers by full-chip lithography simulation. Therefore, experimental full-chip inspection methodologies for
hotspots extraction are necessary in order to construct hotspot management for SPTs. In this work, we applied the D2DB
inspection system with electron beam (EB) to SPTs in hotspot management flow. For the D2DB inspection system, the
NGR-2100 has remarkable features for the full-chip inspection within reasonable operating time. This system provides
accurate hotspot extraction by EB with wider field of view (FOV) than that of SEMs. With the constructed hotspot
management flow, extracted hotspots for SPT involving errors of around 10nm could easily be fed back to fix the wafer
processes and mask data.
We have studied both the mask CD specification and the mask defect specification for spacer patterning
technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since
SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers
involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies
that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication
strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our
experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from
those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction
of line-width roughness (LWR).
We studied the mask defect printability for both opaque and clear defects in the spacer patterning process. The spacer
patterning process consists of the development of photoresist film, the etching of the core film using the photoresist
pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the
core film. The pattern pitch of the spacer film becomes half that of the photoresist. The opaque defect and the clear
defect of the mask, respectively, resulted in an "open-short complex" defect and a short defect in the spacer pattern, The
defect size of both the opaque and clear defect became smaller as the process proceeded from the development to the
core film etching and the spacer pattern fabrication. The decrease of the mask defect printability during the spacer
process is likely to be related to the reduction of the line width roughness (LWR) and to the reduction of mask enhanced
factor (MEF). The acceptable mask defect size was also studied from the viewpoint of the defect printability to the
spacer pattern for both the opaque and clear defect, and found to be 55-60nm, which was relaxed from that in ITRS2007.
Flow of fixing of hot spot induced by optical variation among exposure tools is discussed for quick ramp-up of high volume products. To achieve robust pattern formation for optical variation, following hot spot detection and fixing approaches are introduced: i) at the design stage, hot spot detection within the optical variation space and hot spot fixing by layout modification or OPC optimization, ii) in order to efficiently detect hot spots within the optical variation space, lithography simulation by combinations of optical parameters determined by the design of experiment (DoE), iii) at the manufacturing stage, hot spot fixing by adjustment of optical parameters using the multi-variable optimization to match OPE between the primary and secondary exposure tool.
A spacer patterning technology (SP) has the possibility of extending optical lithography to below 40nm half-pitch devices. Since the spacer patterning process necessitates somewhat more complicated wafer process flow, the CD variation on wafers involves more process error sources compared with conventional exposure patterning process. This implies that, for the spacer patterning process innovation in determining specifications for each unit process is requried. In particular, it is important to determine mask-related specifications in order to select high-end mask fabrication strategies for mask writing tools, mask process development, materials, inspection tools, and so on. The purpose of this paper is to discuss how to consider mask specification in spacer patterning process for 40nm half-pitch and beyond.
We constructed CD budget for spacer patterning technology which is one of the strongest candidates in double
patterning technologies for below 3x nm half pitch generations. In the CD budgeting, three patterning portions of grid
patterns should be considered, namely, "line", "paired space" and "adjoined space", because they have individual
process error sources that affect CD variations. Analysis of the patterning process flow revealed that the amount of CD
variations for positive type spacer patterning technology was in the order of "adjoined space" > "paired space" > "line".
Also, the experimental verifications in CD variations substantiated the constructed CD budget. From the viewpoint of
design for manufacturability (DfM), these process features should be taken into account in the device engineering.
Therefore, for the successful implementation of spacer patterning technology into high-end devices, we propose a cross-
functional development scheme encompassing device technologies and process technologies using the constructed CD
The specification of photomask patterns is defined for each semiconductor device technology node based on the
ITRS (International Technology Roadmap for Semiconductors). The quality of the photomask patterns has been
managed by using a metrology tool for CD (Critical Dimension) and an inspection tool for pattern shape. According
to shrinkage of semiconductor device patterns, the lithography margin has gradually become smaller. Consequently,
the quality of photomask patterns has been managed by observing small lithography margin patterns in addition to
the conventional quality management patterns with the conventional metrology tool. Furthermore, recently, as each
successive device generation has become shorter, rapid improvement of not only turnaround time of photomask
manufacturing but also yield of semiconductor device manufacturing has become necessary. Therefore, the
importance of the flexible mask specifications concept is increasing. The quality of photomask patterns with respect
to the specifications is judged in terms of pass/fail based on the allowable lithography margin. The methodology
is that small lithography margin patterns are selected, micrographs of the selected photomask patterns are acquired by
a metrology tool, photomask pattern contours are extracted with the micrographs, resist patterns exposed on Si wafer
are simulated by using the photomask pattern contours with lithography simulation under actual exposure conditions,
the lithography margin is calculated and the quality of the photomask is judged in terms of pass/fail criteria based on
the lithography margin for each generation, device and layer.
For management of the quality of photomask patterns based on the flexible mask specifications, it is necessary to
measure two-dimensional patterns such as hot-spot patterns for each critical layer in devices having small lithography
margin. Therefore, in order to manage quality in the case of flexible mask specifications, a two-dimensional
photomask pattern contour extraction tool was studied and developed. The photomask pattern contour extraction
tool realizes the combination of acquisition of fine-pixel SEM images of the photomask patterns in wide field and
extraction of photomask pattern contours by using the acquired fine-pixel SEM images.
There have been many reports on the repeatability and reliability of CD and two-dimensional pattern metrology
tools based on the conventional specifications. However, there are very few reports on the repeatability and reliability
of photomask pattern metrology tools based on flexible mask specifications. In this paper, using small lithography
margin patterns, firstly, the fine-pixel SEM images of photomask patterns are acquired. Secondly, contours of the
photomask patterns are extracted with the SEM images. Thirdly, contours of resist patterns on Si wafer are simulated
with lithography simulation under actual exposure condition by using the actual photomask pattern contours. Finally,
the lithography margin is calculated by using FEM (Focus Exposure Matrix) for the simulated contours of resist
patterns. This flow is repeated. The lithography margin with this flow is compared with that of actual exposed
wafers. Repeatability and reliability of the lithography margin is evaluated. As a result, accuracy of the photomask
pattern contour extraction tool is discussed.
We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM . The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account.
Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.