AIMS™ is mainly used in photomask industry for verifying the impact of mask defects on wafer CD in DUV lithography process. AIMS verification is used for D2D configuration, where two AIMS images, reference and defect, are captured and compared. Criticality of defects is identified using a number of criteria. As photomasks with aggressive OPC and sub-resolution assist features (SRAFs) are manufactured in production environment, it is required to save time for identifying reference pattern and capturing the AIMS image from the mask. If it is a single die mask, such technology is truly not applicable. A solution is to use AIMS die-to-database (D2DB) methodology which compares AIMS defect image with simulated reference image from mask design data. In general, simulation needs calibration with AIMS images. Because there is the difference between an AIMS image except a defect and a reference image, the difference must be compensated. When it is successfully compensated, AIMS D2DB doesn’t need any reference images, but requires some AIMS images for calibration. Our approach to AIMS D2DB without calibration image is systematic comparison of several AIMS images and to fix optical condition parameters for reducing calibration time. And we tried to calibrate using defect AIMS image to this approach. In this paper, we discuss performance of AIMS D2DB simulation without calibration images.
In this report, we compared the lithographic performances between the conventional positive tone development (PTD) process and the negative tone development (NTD) process, using the lithography simulation. We selected the MoSi-binary mask and conventional 6% attenuated phase shift mask as mask materials. The lithographic performance was evaluated and compared after applying the optical proximity correction (OPC). The evaluation items of lithographic performance were the aerial image profile, the aerial image contrast, normalized image log slope (NILS), mask error enhancement factor (MEEF), and the bossung curves, etc. The designs for the evaluation were selected the simple contact hole and the metal layer sample design.
193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Multi-patterning of an increasing number of critical layers puts extreme pressure on wafer intra-field overlay, to which mask registration error is a major contributor . The International Technology Roadmap for Semiconductors (ITRS ) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Full characterization of mask registration errors in the active area of the die will become mandatory. It is well-known that differences in pattern density and asymmetries in the immediate neighborhood of a feature give rise to apparent shifts in position when measured by optical metrology systems, so-called optical proximity effects. These effects can easily be similar in magnitude to real mask placement errors, and uncorrected can result in mis-qualification of the mask. Metrology results from KLA-Tencor’s next generation mask metrology system are reported, applying a model-based algorithm  which includes corrections for proximity errors. The proximity corrected, model-based measurements are compared to standard measurements and a methodology presented that verifies the correction performance of the new algorithm.
Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to
EUV lithography. Utilization of 193nm lithography for 45nm and beyond forces the mask shop to produce
complex mask designs and tighter lithography specifications which in turn make process control more
important than ever. High yield with regards to chip production requires accurate process control.
Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and
reliable functionality of any integrated circuit. There are different contributors which impact the total wafer
CDU, mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc.
In this paper, the wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements
in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The
WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second
laser to write intra-volume shading elements (Shade-In ElementsTM) inside the bulk material of the mask. By
adjusting the density of the shading elements, the light transmission through the mask is locally changed in a
manner that improves wafer CDU when the corrected mask is printed.
The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize
CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level.
Mainly we present the method of operation and results for logic pattering by using these two tools.
To improve lithography performance, resolution enhancement technique (RET) such as source mask
optimization (SMO) will be applied to 22 nm node and beyond. We examine if lithography performance is improved
by altering mask 3D topography. In this paper, we report that we have confirmed what topography is effective for
lithography performance improvement in the dense region of 22nm technology node. Since shadowing effect is
strong at the dense region, we focus on sidewall angle that decreases shadowing effect. As a basic analysis, we
evaluate maximum exposure latitude (EL) and mask error enhancement factor (MEEF) of mask 3D topographic
patterns that have various sidewall angles by 3D rigorous simulator. This result shows the increasing of maximum
exposure latitude when changing sidewall angle. As a next step, we fabricate a test mask which has optimized
sidewall angle and the exposure is performed on NA1.30 immersion scanner (Nikon NSR-S610C). Then we compare
wafer printing results and simulation results. These results induce that the optimization of mask 3D topography has a
potential to improve lithographic performance.
In this study, we investigate what kind of mask blank material is optimum for the resolution
enhancement techniques (RET) of leading-edge ArF lithography. The source mask optimization (SMO) is
one of the promising RET in 2Xnm-node and it optimizes mask pattern and illumination intensity
distribution simultaneously. We combine SMO with the blank material optimization and explore the truly
This study consists of three phases. In the first phase, we evaluate maximum exposure latitude
(Max.E.L.) and mask error enhancement factor (MEEF) of fictitious materials that have typical real (n)
and imaginary (k) value of refractive index by 3D rigorous simulator as the basic analysis. The simulation
result shows that there are two high lithographic performance combinations of n and k values; one is
low-n/high-k and the other is high-n/low-k.
In the second phase, we select actual blank material that has similar optical parameters with the
result of the previous phase. The lithographic performance of the selected material is investigated more
precisely. We find that the candidate material has good lithographic performance at the semi-dense pitch.
In the final phase, we create a test mask of this candidate blank material and verify simulation
result by experimental assessment. The exposures are performed on NA1.30 immersion scanner (Nikon
NSR-S610C). The experimental result shows the improvement of Max.E.L. in head to head type pattern.
This study will discuss the potential of blank material tuning for the ArF lithography extension.
At 32nm node and beyond, a common approach in defect inspection (high resolution inspection mode) to
cope with aggressively OPCed mask patterns including SRAFs, is the utilization of small pixel size
inspection. In fact the sensitivity is increased by using smaller pixel size for the high resolution
inspection, but at the same time the throughput of the defect inspection tool falls.
In this paper, we propose that one of the solutions to improve inspection throughput is pixel migration.
KLA-Tencor's TeraScan XR improves SNR (Signal to Noise Ratio) for higher sensitivity as
comparison with TeraScanHR, so that pixel migration is possible. For tool performance confirmation,
TeraScanXR has improved in defect sensitivity and SRAF MRC (Mask Rule Check) limitation as
comparison with TeraScanHR. We confirmed that pixel migration is one of the solutions to control
inspection time growth of next generation mask. For printability simulation of pixel migration, we
confirmed the possibility of Brion's Mask-LMC (Mask-Lithography Manufacturability Check) defect
classification by lower SNR image. For experiment to achieve higher sensitivity, we confirmed defect
sensitivity improvement with experimental condition and considered the model to achieve higher sensitivity.
193nm-immersion lithography is the most promising technology for 32nm-node device fabrication. At the 32nm
technology-node, the performance of photomasks, not only phase-shift masks but also binary masks, needs to be improved,
especially in "resolution" and "CD accuracy". To meet sub-100nm resolution with high precision, further thinning of resist
thickness will be needed.
To improve CD performance, we have designed a new Cr-on-glass (COG) blank for binary applications, having OD-3
at 193nm. This simple Cr structure can obtain superior performance with the conventional mask-making process. Since the
hardmask concept is one of the alternative solutions, we have also designed a multilayered binary blank.
The new COG blank (NTARC) was fully dry-etched with over 25% shorter etching time than NTAR7, which is a
conventional COG blank. Thinner resist (up to 200nm) was possible for NTARC. NTARC with 200nm-thick resist showed
superior resolution and CD linearity in all pattern categories.
On the other hand, the multilayered binary stack gives us a wide etching margin for several etching steps. Super thin
resist (up to 100nm) was suitable by using a Cr-hardmask on a MoSi-absorber structure (COMS). The COMS blanks
showed superior performance, especially in tiny clear patterns, such as the isolated hole pattern.
We confirmed that these new photomask blanks, NTARC and COMS, will meet the requirements for 32nm-node and
beyond, for all aspects of mask-making.
The mask-making process for 45nm-node and beyond demands higher resolution and CD accuracy. To meet the requirements, the multi-layer resist system is developed as one of the solutions. BIL (Bottom Insulating Layer) can correct the profile of CAR (Chemically Amplified Resist). CAR shows profile degradation by photo-acid loss at the boundary of chrome and resist. The photo-acid loss induces excess footing in positive-tone CAR and under-cutting in negative-tone CAR. BIL reduced the profile degradation to less than half of the conventional resist system. BIL requires no extra mask process steps. Final CD linearity of isolated lines was improved by BIL. It is very beneficial for the patterning of sub-resolution assist features. Moreover, BIL with a hard-mask layer showed superior dry-etching bias performance.
The CD requirements for the 45nm-node will become tighter so as it will be difficult to achieve with 65nm node
technologies. In this paper, a method to improve resolution by using DRECE (Dry-etching Resistance Enhancement
bottom-Coating for Eb) will be described. After all, DRECE has five times as high dry-etch resistance than the EB resist,
and this enables to accept higher anisotropic dry etching condition. By optimizing dry etching conditions, the CD
iso-dense bias dropped to 1/3 and the CD shift was reduced to 1/2. Also, there was no negative effect to CD uniformity.
From these results, we propose the use of DRECE for the 45nm-node technology.