Electron Projection Lithography (EPL) provides a fundamental advantage in resolution. In this paper, resolution improvement of EPL masks and minimum resolution in EPL exposure are addressed. In order to improve the mask resolution, we applied membranes thinner than typical thickness of 2 um to e-beam scattering layers of the EPL stencil masks. Although strength of the membrane generally deteriorates with decrease in the membrane thickness, the EPL masks having 1-um-thick scattering layers were feasibly fabricated. Reduction of the membrane thickness down to 1 um considerably improved the mask minimum feature size to resolve 120-nm holes and 80-nm lines which corresponded to 30 nm and 20 nm on wafer dimension, respectively, in the 4x demagnification EPL exposure system. The application of the 1-um-thick membrane simultaneously brought the high resolution and good pattern qualities: CD uniformity less than 10 nm in 3σ with pattern sidewall angle range of 90° ± 0.2°. We performed wafer exposure experiments in combination of the EPL exposure tool NSR-EB1A (Nikon) and the 1-um-thick membrane mask, and obtained the resolution performance of 40-nm holes on the wafer. We conclude that the application of the 1-um-thick membrane to the e-beam CD qualities. The exposure resolution of 40-nm holes on the wafer reveals the EPL exposure system to be a potential solution for contact layers in the future technology node.
We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.
Stencil masks for electron projection lithography (EPL) require peculiar patterns as perforations in a thin membrane. The stencil pattern accuracy of a conventional mask with 1-mm subfields and a new geometry mask with 4-mm subfields was evaluated and compared. No significant influence of the mask geometry on most of critical dimension (CD) specifications was observed. The stencil patterns in both geometry masks had vertical sidewalls ~ 90° with angle range less than 0.3° and CD uniformity of ~12 nm (3σ) across the mask. CD linearity is also similar for both geometry masks. On the other hand, enlarging the membrane windows considerably increased CD deterioration and image placement (IP) distortion within individual membranes. A practical 4 mm-window mask requires solution to this issue. The stencil pattern accuracy is, however, acceptable level for not only the 1 mm-window mask but also the 4 mm-window mask at current EPL development status. According to the evaluation of the stencil pattern accuracy, pattern specification of the EPL mask for 45-nm node would be achieved with further process optimization despite of its peculiarity in pattern structure.
Large window-size membranes for stencil masks are required to increase the throughput of electron projection lithography (EPL) and low-energy electron projection lithography (LEEPL). In this paper, image placement (IP) accuracy and methodology for correcting stress-induced distortions on 4 X EPL masks are addressed. Although the average of local IP errors (| mean | + 3σ) for reference features across an entire 1mm-window EPL mask is 13.4 nm, the average of errors across an entire 4mm-window EPL mask increases to 20.4 nm, which could be reduced to the required budget with further study on EB writing accuracy or IP corrections. In addition we evaluate local IP errors on 4mm-window mask due to pattern gradients by measuring the placement errors at the edge of dense hole arrays. Applying the correction for stress-induced distortions to EB data, we can reduce the placement errors for dense features to 4.6 nm, which is less than the 10 nm budget allocated for 4mm-window EPL mask at the half-pitch features of 45 nm node. For the global IP, only the measurement repeatability of 7.8 nm contributes to the global IP budget measuring all the global position over an entire 4mm-window EPL mask. And we can meet the required global IP budget. Finally, IP accuracy for a single membrane is also presented, showing the IP error is 24.5 nm (| mean | + 3σ), which compares with that of COSMOS type LEEPL mask. Methodology of measuring the position data on a single membrane, however, remains to be developed.
Two types of strut-supported low energy electron-beam proximity projection lithography (LEEPL) masks which are grid-type mask and COSMOS-type mask, were investigated for Global image placement (IP). First, we evaluated the dynamic repeatability measurement performance for global IP, measuring a same mask 10 times on a 46 x 46 mm pattern area by using LEEPL electrostatic chuck (ESC). The measurement repeatability for grid type and COSMOS type were 5.1/7.8 nm and 4.4/5.8 nm in x/y directions respectively. And then global in-plane distortion (IPD) of COSMOS type masks with various stress and flatness were measured. The global IPD of a COSMOS-type mask with a low stress of 10 MPa and a flatness of 3.1 μm was 6.5/6.4 nm in x/y directions, which is negligible assuming the measurement repeatability. Finally the global IPs of the two-type masks were measured. The global IPs for the grid-type and COSMOS-type were 24.5/15.7 nm and 23.2/16.4 nm in x/y directions respectively. Thus we confirmed that the global IP obtained meet the required value of less than 30 nm.
The challenges in fabricating next-generation lithography (NGL) masks are distinct from those encountered in optical technology. The masks for electron proximity lithography, as well as those for ion and electron projection, use freestanding membranes incorporating layers that are different from the traditional chrome-on-glass photomask blanks. As a promising NGL technology, low-energy electron-beam proximity-projection lithography (LEEPL) will be subject to strict error budgets, requiring high pattern placement accuracy. Meeting these stringent conditions will necessitate an optimization of the design parameters involved in the mask fabrication process. Consequently, comprehensive simulations can be used to characterize the sources of the mechanical distortions induced in LEEPL masks during fabrication, pattern transfer, and mounting. For this purpose, finite element (FE) structural models have been developed to identify the response of the LEEPL mask during fabrication and chucking. Membrane prestress, which is used as input in the FE models, was measured on a 200-mm test mask and found to low in magnitude with excellent cross-mask uniformity. The numerical models were also validated both analytically and experimentally considering intrinsic and extrinsic loading of the mask. Finally, simulations were performed to predict the response of the LEEPL mask during electrostatic chucking. FE results indicate that the mask structure is sufficiently stiff to remain relatively flat under gravitational loadings. The results illustrate that mechanical modeling and simulation can facilitate the timely and cost-effective implementation of the LEEPL technology.
Membrane stress control is one of the challenges for the commercial success of the stencil masks, such as electron projection lithography (EPL) and low energy electron-beam proximity projection lithography (LEEPL), since a stencil mask has perforation patterns in a membrane with image placement meeting stringent error budget. First, stress-induced distortions of stencil mask membranes were simulated by a finite element method (FEM). Second, we showed how the membrane stress varies with dopant concentration, using a pressure bulge method for stress measurements of die-size specimens. The results show doping SOI substrates provide a low-stress membrane. Third, correlation between the pressure bulge method and resonance frequency technique (RFT) was investigated and showed acceptable agreement. Fourth, stress distribution measurements were taken using the RFT for a low-stress 200-mm EPL mask. Average stress value and cross-mask stress variations were 11.2 MPa and ± 1.3 MPa respectively. Therefore, we revealed reliable stress distribution data across a 200-mm EPL mask and confirmed the doping method using SOI substrate is proper approach to fabricate a low-stress 200-mm stencil mask, with high uniformity of membrane stress, for EPL and LEEPL.
We focus on stencil mask technologies for the next generation lithography (NGL) options such as electron projection lithography (EPL) and low energy electron-beam proximity projection lithography (LEEPL). For the production of high-quality stencil masks, we selected silicon-on-insulator (SOI) substrate as desirable stencil mask material because of its availability and quality. We showed how the membrane stress varies with dopant concentration and our proposed theoretical prediction on stress dependency on dopant concentration is consistent with experimental data. From the experimental data and prediction, doping method using SOI substrates proved to be able to produce membranes with stress of less than 10 MPa. We also presented how the out-of-plane distortions (OPD) within a subfield depend on the doping profile and cantilever beams with a length of 200 um remained flat. And then we measured the image placement (IP) errors within a subfield on a 200-mm EPL mask, which was less than 20 nm. Finally we employed the doping method to LEEPL mask and presented stress data. Therefore, we confirmed the doping method using SOI substrate is proper approach to fabricate low-stress stencil masks for EPL and LEEPL.
We developed 200-mm stencil masks for electron projection lithography (EPL) by using silicon-on-insulator (SOI) substrates. Stress of a 2-μm-thick single crystalline silicon membrane, where patterns were fabricated as openings, was controlled around 10 MPa by adjusting concentration of impurities doped into the SOI layer. Boron and phosphorus were investigated as doping impurities, and it was confirmed that doping both elements were capable of stress control. For forming struts that supported the thin membrane, a time multiplexed etch method was applied. Control of the deep etch parameters made it possible for the SiO2 stopper layer not to be etched through even if its thickness was sub-microns. To fabricate pattern openings in the membrane, reactive ion etching with high-density plasma was applied and lines down to 140 nm was fabricated in a 200-mm mask. Image placement distortion within a subfield was measured across the 200-mm mask and magnitudes of the image placement distortion were typically ~15 nm (3σ). A 200-mm EPL stencil mask having Selete's actual 70-nm design-rule system on chip (SoC) device pattern was successfully fabricated. We confirmed that the SOI substrates had potential abilities as initial material for 200-mm stencil mask fabrication.