Inpria is pioneering a novel approach to EUV photoresist. Directly patternable metal oxide thin films have shown resolution better than 10nm half-pitch, with robust etch resistance, and efficient use of photons through high EUV absorbance. Inpria’s Gen2 photoresists are cast from commonly used organic coating solvents and are developed in typical negative tone develop (NTD) organic solvents. This renders them compatible with CLEAN TRACK LITHIUS Pro-EUV coater/developer system (Tokyo Electron Limited; TEL) and solvent drains. The presence of metal in the photoresist demands additional scrutiny and process development to minimize contamination risks to other tools and wafers. In this paper, we review progress in developing coat processes that reduce metal contamination levels below typical industry levels. We demonstrate minimization of trace metals contamination from wafer-to-coater/developer, and wafer-to-wafer from the spin coat process. This will also include results from surface analyses of frontside edge exclusion and backside of wafer using best-known analytical methods. In addition, we discuss results of coat uniformity and defectivity optimization. Wet clean compatibility and dry etch rate by using conventional Si-ARC/OPL etching recipe will also be presented. In conjunction with this work, we identify potential contamination pathways and means for managing contamination risk. We furthermore review equipment compatibility issues for using Inpria’s metal oxide photoresists.
Recently there has been a great deal of effort focused on increasing EUV scanner source power; which is correlated to increased wafer throughput of production systems. Another way of increasing throughput would be to increase the photospeed of the photoresist used. However increasing the photospeed without improving the overall lithographic performance, such as local critical dimension uniformity (L-CDU) and process window, does not deliver the overall improvements required for a high volume manufacturing (HVM). This paper continues a discussion started in prior publications [Ref 3,4,6], which focused on using readily available process tooling (currently in use for 193 nm double patterning applications) and the existing EUV photoresists to increase photospeed (lower dose requirement) for line and space applications. Techniques to improve L-CDU for contact hole applications will also be described.
Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.
In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
EUV lithography is one of the main candidates for enabling the next generation of devices, primarily by enabling a lithography process that reduces complexity, and eventually, cost. IBM has installed the latest tool sets at the IBM EUV Center of Excellence in Albany to accelerate EUV lithography development for production use. Though the EUV cluster is capable of enabling the pitch requirements for the 7nm node, the dimensions in question represent a new regime in defectivity. Additionally, new classes of patterning materials are being explored, for which there is very little known up-front regarding known defect mechanisms. We will discuss the baseline cluster performance and the improvement strategy in terms of defectivity and pattern collapse in this paper by utilizing coater/developer techniques based on the new platform.