To cope with the explosive growth of IP traffic, we must increase both the link capacity between nodes and the node throughput. These requirements have stimulated research on photonic networks that use optical technologies. Optical packet switching (OPS) is an attractive solution because it maximizes the use of the network bandwidth. The key functions in achieving such networks include synchronization, label processing, compression/decompression, regeneration, and buffering for high-speed asynchronous optical packets. However, it is impractical to implement such functions by using all-optical approaches. We have proposed a new optoelectronic system composed of a packet-by-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The OCG provides a single optical pulse synchronized with the incoming packet, and the SPC carries out a parallel conversion of the incoming packet. The parallel converted data are processed in the smart CMOS circuit, and reconstructed into an optical packet by the photonic PSC. Our system makes it possible to carry out various functions for high-speed asynchronous optical packets. This paper reviews our recent work on high-speed optical packet processing technologies such as buffering, packet compression/decompression, and label swapping, which are key technologies for constructing future OPS networks.
We present a photonic random access memory (RAM) that can write and read high-speed asynchronous burst optical packets freely by specifying addresses. The photonic RAM consists of an optical clock-pulse generator, an all-optical serial-to-parallel converter, a photonic parallel-to-serial converter, all developed by us, and a CMOS RAM as a storage medium. Unlike conventional optical buffers, which merely function as optical delay lines, the photonic RAM provides various advantages, such as compactness, large capacity, long-term storage, and random access at an arbitrary timing for ultrafast asynchronous burst optical packets. We experimentally confirm its basic operation for 40-Gbit/s 16-bit optical packets.
We propose novel ultrafast photonic interfaces for use in storage networking based on all-optical serial-to-parallel and photonic parallel-to-serial conversion. We confirm their operation with 40-Gbit/s 16-bit optical data using compact modules and a potential bandwidth of over 100 Gbit/s. We realize a photonic random access memory (RAM) by sandwiching a CMOS RAM with these two interfaces and achieve the storage and read-out of 40-Gbit/s 16-bit optical data. We also discuss the advantages of the interfaces and their possible applications to storage networking such as the real-time remote back-up of huge quantities of data, disaster recovery and video communication systems.
A new electrical parallel-to-serial converter (PSC) is proposed for optical communication networks. The PSC uses a simple circuit scheme that markedly reduces the fall time of a ordinary MSM-PD without degrading either its sensitivity or ease of fabrication. An InP-based 4:1 PSC is shown to convert 4-ch parallel electrical signals into a serial 10-Gbit/s 4-bit electrical signal when MSM-PDs in the PSC are optically triggered. It has several advantages including support of burst signal input, low driving voltage, compactness, ease of fabrication, and low power consumption. The electrical PSC is used in a new photonic PSC. By effectively combining electrical multiplexing with optical multiplexing, the photonic PSC can generate a 40-Gbit/s 16-bit optical packet from 16-ch parallel electrical signals with frame rates of 40 MHz. The electrical PSC is also applied to a label comparator for bypass/drop self-routing of optical packets. The label comparator, consisting of the 4:1 PSC and an electroabsorption modulator (EAM), properly processed 10-Gbit/s burst optical packets with no preamble even when a local address was changed at 40 MHz.