The computer cost for mask data processing grows increasingly more expensive every year.
However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which
originally was used exclusively for digital image processing has been used in many fields of
numerical analysis. We developed mask data processing techniques using GPUs together with
distributed processing that allows reduced computer costs as opposed to a distributed processing
system using just CPUs.
Generally, for best application performance, it is important to reduce conditional branch
instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize
memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light
intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU
implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by
fracturing input data and balancing a computational road for each CPU, we have put the powerful
distributed computing into practice.
Furthermore we have investigated not only the improvement of software performance but also how
to best balance computer cost and speed, and we have derived a combination of the CPU hosts and
the GPU devices to maximize the processing performance that takes computer cost into account .
We have also developed a recovery function that continues OPC processing even if a GPU breaks
down during mask data processing for a production. By using the GPUs and distributed
processing, we have developed a mask data processing system which reduces computer cost and has
We compared a simulator's predictions with the critical dimension (CD) value measured on the
wafer. We used sub resolution assist features (SRAF) in the experiment to keep the focus margin, the
minimum size of the mask was small and comparable with the absorber's thickness. Therefore, it
seems that we need a rigorous model and a variety of parameters for high prediction accuracy.
We investigated the prediction error and found its behavior was not complicated. The dependence
of the prediction errors was related to the space until the next feature, but the relationship was not
linear; rather, it went up and down periodically like a Bessel function. This fact gave us the idea that it
might be possible to improve the simulation accuracy by using a special convolution kernel but not a
We used a complementary kernel and tried to find a suitable shape to match the prediction error.
The convolution kernel consisted of a complex number in order to represent phase change and
amplitude loss. The kernel was applied to the simulator's mask plain. The results showed a significant
improvement in simulation accuracy and a reduction in the route mean square (RMS) of the CD fitting
error for all features with or without SRAFs.
We used this model for optical proximity correction (OPC) and verified its accuracy with a printed
wafer image. The range of the final CD variation of 40 nm line on the wafer was 1.9 nm, and the
model also showed good agreement with the experimental two-dimensional feature shape.
The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well
used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This
technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this
double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique
without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method,
attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new
double exposure method is effective for random logic devices which have various pattern pitches by the optimization of
dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated.
From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is
wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense
pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is
found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double
exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM)
rule that required the severe line width control is placed at single direction is proposed to realize the new double
exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as
conventional method with alt-PSM for gate layer of 45 nm logic devices.
Patterning of contact/via is a difficult issue for the optical lithography for each successive generation of LSIs. We examined a number of approaches to obtain a large process window and found that a dry ArF exposure tool with a large depth of focus (DOF) can form 100 nm contact holes. Our experimental results show that enough DOF can be obtained for various layouts by using sub-resolution assist feature (SRAF) technology and a unique illumination technology.
We proposed a design-friendly DFM rule intended to improve circuit performance. To reduce variations in the gate length, we applied active usage of preferred gate spaces and optimized the lithographic conditions. We selected the spaces to take into account the layouts that are used most frequently in actual design, so that many designers who are worrying about chip area and performance can follow the rule. The effect of our method was evaluated for 65-nm node technology. From the viewpoint of gate length, parallel usage of design following the rule and optimization lead to an 8% decrease in variation, and a 38% decrease in the mean difference from the targeted gate length. We also evaluated the effect on delays using an accurate method that can treat both statistical and systematic variation. The difference in the average delay from the targeted value was reduced from about 1% to less than 0.1%, and a 10% improvement in delay variation was observed.
Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.
Phase shifter edge lithography (double-exposure method) provides improved image contrast and lithographic resolution. However, it is subject to the problems of optical proximity effects. Therefore, to make this technique practical for use in device manufacturing, it is necessary to understand the characteristics of optical proximity effects and through such understanding establish a practical OPC (Optical Proximity Correction) method to correct them. Since the size of both the phase shift mask (PSM) and the trim mask (a mask used to form a rough gate pattern) significantly affect the wafer CD (critical dimension), an OPC tool which takes the layout of the two masks into account is required. Due to the difficulty in describing a rule-table for both masks, a model-based approach is a suitable means to develop such a tool. A PSM and a trim mask are used to calculate aerial images. In a double-exposure approach, however, mask shape does not define the desired shape. Therefore, an additional layer which defines the desired shape has been introduced. The desired shape is also used to consider the etching effect, which is described in a rule-table and applied to the original layout. With this approach, the desired shape defines the resist shape. To improve computing time, we apply model-based OPC only to specified areas, and rule-based OPC outside of those areas. Because of the large amount of data that must be processed, the designed layout is divided into fractions and compute on a multi-processor system. Previously, we reported improvements in pattern-matching methods to reduce the simulation time. In this paper, we report full-chip- correction performance and results of OPC technology.
Lithographic DRC which takes optical interference effect into account can find and solve the related optical problems beforehand. That is, it can detect the weak points of pattern layout with respect to optical intensity and identify problems which would have remained unnoticed with geometric DRC. Usual approach comparing the aerial images with the intended shape of pattern takes a quite long time. To improve the processing time of DRC, we set verification points on pattern's edge and classified the individual points by analyzing surroundings within optical interference range. With this approach, it becomes possible to reduce the calculation time, since only a one-time calculation is required for each unique point. Comparing designed pattern layout with its aerial image may result in hundreds of small errors near small jogs or at the corner of patterns. To eliminate these small errors, we used a rounded pattern layout as the intended shape of the resist. Well-fitted condition is used for the aerial image simulation, that is, defocused aerial images and the threshold model are employed for the prediction of the shape of resist. Using these methods, we achieved an improvement with respect to both processing time for DRC and obtained accuracy. We applied lithographic DRC to actual device patterns, and we could verify that it was possible to detect the point with coupling, shortening and less margin.
The optical proximity effect becomes significant near the practical resolution limit of photolithography, depending on the wavelength and numerical aperture of the stepper. Recently, VLSI design rules have almost reached their limits. Larger ICs cannot be designed and be manufactured without using a lithographic DRC (design rule check) tool or an OPC (optical proximity correction) tool. Therefore, it has become necessary to develop a technology which can accurately predict resist features from the designed circuit layout. We studied deviation in both the line width and the length due to proximity effect and investigated the phenomena. Also we developed a technology which can accurately predict the behavior of the proximity effect from an aerial image. This technology is based on a simple threshold model. We optimized the calculations for an aerial image and the threshold of intensity in order to predict deviations in the line width and length. We also considered the profile of an aerial image to predict the critical point. The calculations for an aerial image and threshold which we optimized in this manner can be used to predict 2D patterns.