Proc. SPIE. 10957, Extreme Ultraviolet (EUV) Lithography X
KEYWORDS: Antireflective coatings, Etching, Silicon, Scanning electron microscopy, Photoresist materials, Extreme ultraviolet, Line width roughness, Extreme ultraviolet lithography, System on a chip, Photoresist developing
Tri-layer processes, which typically consist of photoresist, Si containing anti-reflective coating (Si-ARC) and spin on carbon (SOC), have been widely used since ArF immersion lithography. Continually reduced pattern dimensions need thinner photoresist films due to the common phenomenon of post-develop line collapse with higher aspect ratios. Consequently, it has been necessary to enhance pattern transfer performance after etching with such tri-layer processes. Successfully implementing tri-layer processes requires consideration of issues such as increased process steps, cost, and other inherent limitations of pattern transfer enhancement with a more complicated stack. In this work, we present a hemicellulose SOC material with the outstanding advantage of Si etch selectivity greater than 15. Hemicellulose SOC could significantly reduce pattern transfer limitations for etching, therefore the benefits of processing higher aspect ratio structures can be more easily achieved. Herein, we investigate the hemicellulose SOC lithography performance using resolution, sensitivity, and line width roughness as metrics. Also, we demonstrate these lithography performances through the etching. During the conference, we will discuss the potential issues of next generation processes using ArF immersion and EUV lithography.
Regarding 3D semiconductor devices, one of difficulties is hardmask process for deep memory holes because of expensive process cost. To overcome this issue, cost effective hardmask process concept using hemicellulose SOC is newly proposed by spin-coat process and improved hardmask technology of hemicellulose SOC (made from bio-based green chemistry material). In this study, deep holes of micron scale were made after under layer RIE using hemicellulose SOC and reactive hemicellulose hardening process (R2H). RIE selectivity was extremely improved up to 65 by optimization of R2H strong process. The results show the feasibility of cost effective deep memory hole process for 3D devices. Additionally, EUV patterns (Hole CD of 24nm and L/S of hp18nm) in under layer were obtained by Hemicellulose SOC and R2H. Its aspect ratio was 15. The fine patterning results show a big potential for next generation memory and logic device processes.