Hot spot fixing (HSF) method has been used to fix many hot spots automatically. However, conventional HSF
based on a biasing based modification is difficult to fix many hot spots under a low-k1 lithography condition. In this
paper we proposed a new HSF, called configurable hotspot fixing system. The HSF has two major concepts. One is a
new function to utilize vacant space around a hot spot by adding new patterns or extending line end edges around the hot
spot. The other is to evaluate many candidates at a time generated by the new functions. We confirmed the proposed
HSF improves 73% on the number of fixing hot spots and reduces total fixing time by 50% on a device layout equivalent
to 28nm-node. The result shows the proposed HSF is effective for layouts under the low-k1 lithography condition.
A practical flare-aware optical proximity correction (OPC) tool for full-chip level has been developed for
upcoming extreme ultraviolet lithography (EUVL). The conventional flare-aware OPC method for EUVL is unsuitable
for practical use because it requires enormous time for lithography simulation to compensate for the long-range flare
effect. By separating the lumped flare-aware OPC step into (1) the OPC step and (2) the flare correction step, the runtime
required for lithography simulation is reduced to 1% by applying the same OPC for the identical pattern at different
positions in step 1. And we found that there is a linear relation between amount of flare and correction bias for each
pattern variation. Using this relation, a fast rule-based correction method can be adopted in step 2 without deterioration
of correction accuracy for any pattern variation. Our new correction tool reduces the run-time to 1/70, which means it is
the same as in the case of optical lithography for full-chip level, and also satisfies the target OPC residual of ±1nm.
Consequently, it has been demonstrated that our new correction is practical and promising for the full-chip in EUVL in
terms of run-time and correction accuracy.
Based on an acceptable wafer critical dimension (CD) variation that takes device performance into consideration, we
presented a methodology for deriving an acceptable mask defect size using defect printability -. The defect
printability is measurable by Aerial Image Measurement System (AIMS<sup>TM</sup>) and simulated by lithography simulation
without exposure. However, the defect printability of these tools is not always the same as the actual one. Therefore, the
accuracy of these tools is confirmed by fabricating the programmed defect mask and exposing this mask on wafer.
Advanced Binary Film (ABF) photomask has recently been studied as a substitute for the conventional MoSi phase shift
mask. For ABF photomask fabrication, mask performance for process and guarantee for mask defects by repair and
inspection are important. With regard to the mask performance, the ABF photomask has high performance in terms of
resolution of pattern making, placement accuracy, and cleaning durability . With regard to the guarantee for mask
defects, it has already been confirmed that the defect on the ABF photomask is repairable for both clear and opaque
defects. However, it has not been evaluated for inspection yet. Therefore, it is necessary to evaluate the defect
printability, to derive the acceptable mask defect size, and to confirm the sensitivity of mask inspection tool.
In this paper, the defect printability of the ABF photomask was investigated by the following process. Firstly, for opaque
and clear defects, sizes and locations were designed as parameters for memory cell patterns. Secondly, the ABF
programmed defect mask was fabricated and exposed. Thirdly, mask defect sizes on the ABF programmed defect mask
and line CD variations on the exposed wafer were measured with CD-SEM. Finally, the defect printability was evaluated
by comparing the correlation between the mask defect sizes and the wafer line CD variations with that of the AIMSTM
and the lithography simulation. From these results, the defect printability of AIMS<sup>TM</sup> was almost the same as the actual
one. On the other hand, the defect printability of the lithography simulation was relaxed from the actual one for the
isolated defect types for both clear and opaque defects, though the defect printability for the edge defect types was
almost the same. Additionally, the acceptable mask defect size based on the actual defect printability was derived and
the sensitivity of the mask inspection tool (NPI-7000) was evaluated. Consequently, the sensitivity of the NPI-7000 was
detectable for the derived acceptable mask defect size. Therefore, it was confirmed that the ABF photomask could be
guaranteed for mask defects.
Computational spacer patterning technology (SPT) has been developed for the first time to address the
challenges concerning hotspots and mask specifications in SPT. A simulation combined with a lithography, etching and
deposition model shows the strong correlation of 0.999, 0.993, 0.980 with the experimental critical dimension (CD),
mask error-enhancement factor (MEEF) and defect printability through a series of spacer processes, respectively.
Furthermore, a design for manufacturability (DfM) flow using computational SPT can find hotspots caused by spacer
patterning processes as well as those caused by lithography process and help designers make the circuit layout more
robust. Besides, a newly defined MEEF and defect printability, which are primary metrics for mask specification, can be
predicted so accurately by using computational SPT that the new scheme to determine appropriate mask specifications is
shown to be feasible under the spacer patterning process condition. Thus, computational SPT is found to be promising
for addressing the challenges concerning hotspot removal and mask specification in the upcoming 20-30nm node and
We introduce techniques of flare compensation for Extreme Ultraviolet Lithography that can reduce the calculation time
of a flare map and flare correction. In the first approach, the range of a flare point spread function is divided into several
regions and the size of meshes for the flare map in each region is selected. In the second approach, the size of the mask
pattern is controlled by referring to the flare map in the mask-making process. In the third approach, dosage of each
point in a mask corresponding to the flare map is modulated when transferring the mask pattern onto the resist. Use of
these approaches in the proper combination is effective for TAT reduction and accuracy of the flare compensation.
We obtained the acceptable mask defect size for both opaque and clear defects in the spacer patterning process using the
fail-bit-map analysis and a mask with programmed defects. The spacer patterning process consists of the development of
photoresist film, the etching of the core film using the photoresist pattern as the etching mask, the deposition of a spacer
film on both sides of the core film pattern, and the removal of the core film. The pattern pitch of the spacer film becomes
half that of the photoresist. Both the opaque defect and the clear defect of the mask resulted in a short defect in the spacer
pattern. From the fail-bit-map analysis, the acceptable mask defect size for opaque and clear defects was found to be
80nm and 120nm, respectively, which could be relaxed from that in ITRS2008. The difference of the acceptable mask
defect size for opaque and clear defects comes from the difference of the defect printability at the resist development.
Novel optical proximity correction (OPC) and design for manufacturability (DfM) methodology for threedimensional
(3D) memory device is proposed to overcome emerging hotspot issues caused by larger process proximity
effect (PPE) due to unavoidable high-aspect patterning process. To realize robust pattern formation for lithography and
reactive-ion etching (RIE) processes, the following methodologies are introduced: i) OPC is carried out by using
averaged or designed optics not ideal to make robust pattern formation for optical variation of exposure tool, ii)
lithography compliance check (LCC) is done under the worst optical condition to detect hotspots induced by optical
variation of exposure tool, and modification of layout and OPC condition is performed to remove hotspots, iii) hotspots
induced by RIE process are checked by using etching simulation with empirical RIE model, and modification of layout,
PPC and OPC scheme is performed to remove hotspots. In this study, it is confirmed that our proposed novel OPC and
DfM methodology is promising for robust pattern formation in upcoming 3D memory device.
We have studied both the mask CD specification and the mask defect specification for spacer patterning
technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since
SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers
involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies
that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication
strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our
experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from
those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction
of line-width roughness (LWR).
We studied the mask defect printability for both opaque and clear defects in the spacer patterning process. The spacer
patterning process consists of the development of photoresist film, the etching of the core film using the photoresist
pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the
core film. The pattern pitch of the spacer film becomes half that of the photoresist. The opaque defect and the clear
defect of the mask, respectively, resulted in an "open-short complex" defect and a short defect in the spacer pattern, The
defect size of both the opaque and clear defect became smaller as the process proceeded from the development to the
core film etching and the spacer pattern fabrication. The decrease of the mask defect printability during the spacer
process is likely to be related to the reduction of the line width roughness (LWR) and to the reduction of mask enhanced
factor (MEF). The acceptable mask defect size was also studied from the viewpoint of the defect printability to the
spacer pattern for both the opaque and clear defect, and found to be 55-60nm, which was relaxed from that in ITRS2007.
Flow of fixing of hot spot induced by optical variation among exposure tools is discussed for quick ramp-up of high volume products. To achieve robust pattern formation for optical variation, following hot spot detection and fixing approaches are introduced: i) at the design stage, hot spot detection within the optical variation space and hot spot fixing by layout modification or OPC optimization, ii) in order to efficiently detect hot spots within the optical variation space, lithography simulation by combinations of optical parameters determined by the design of experiment (DoE), iii) at the manufacturing stage, hot spot fixing by adjustment of optical parameters using the multi-variable optimization to match OPE between the primary and secondary exposure tool.
Robust optical proximity correction (OPC) and design for manufacturability (DFM) methodology for optical
variation among exposure tools is proposed. It is demonstrated that application of the methodology improves standard
deviation of CD difference for target CD by 33% compared with the case of using the conventional methodology. Under
the low-k1 lithography condition, hot spots induced by optical variation among exposure tools delay ramp-up of
production of high-volume products. To realize robust pattern formation for all exposure tools, the following new
methodologies are introduced : i) OPC modeling methodology using actual optics of primary tool, ii) OPC processing
methodology using averaged or designed optics, iii) at the design stage, hot spot detection within the optical variation
space centered on average or designed optics and hot spot fixing by layout modification or OPC optimization, iv) at the
manufacturing stage, hot spot detection using actual optics and hot spot fixing by optical adjustment of troubled tool.
The specification of photomask patterns is defined for each semiconductor device technology node based on the
ITRS (International Technology Roadmap for Semiconductors). The quality of the photomask patterns has been
managed by using a metrology tool for CD (Critical Dimension) and an inspection tool for pattern shape. According
to shrinkage of semiconductor device patterns, the lithography margin has gradually become smaller. Consequently,
the quality of photomask patterns has been managed by observing small lithography margin patterns in addition to
the conventional quality management patterns with the conventional metrology tool. Furthermore, recently, as each
successive device generation has become shorter, rapid improvement of not only turnaround time of photomask
manufacturing but also yield of semiconductor device manufacturing has become necessary. Therefore, the
importance of the flexible mask specifications concept is increasing. The quality of photomask patterns with respect
to the specifications is judged in terms of pass/fail based on the allowable lithography margin. The methodology
is that small lithography margin patterns are selected, micrographs of the selected photomask patterns are acquired by
a metrology tool, photomask pattern contours are extracted with the micrographs, resist patterns exposed on Si wafer
are simulated by using the photomask pattern contours with lithography simulation under actual exposure conditions,
the lithography margin is calculated and the quality of the photomask is judged in terms of pass/fail criteria based on
the lithography margin for each generation, device and layer.
For management of the quality of photomask patterns based on the flexible mask specifications, it is necessary to
measure two-dimensional patterns such as hot-spot patterns for each critical layer in devices having small lithography
margin. Therefore, in order to manage quality in the case of flexible mask specifications, a two-dimensional
photomask pattern contour extraction tool was studied and developed. The photomask pattern contour extraction
tool realizes the combination of acquisition of fine-pixel SEM images of the photomask patterns in wide field and
extraction of photomask pattern contours by using the acquired fine-pixel SEM images.
There have been many reports on the repeatability and reliability of CD and two-dimensional pattern metrology
tools based on the conventional specifications. However, there are very few reports on the repeatability and reliability
of photomask pattern metrology tools based on flexible mask specifications. In this paper, using small lithography
margin patterns, firstly, the fine-pixel SEM images of photomask patterns are acquired. Secondly, contours of the
photomask patterns are extracted with the SEM images. Thirdly, contours of resist patterns on Si wafer are simulated
with lithography simulation under actual exposure condition by using the actual photomask pattern contours. Finally,
the lithography margin is calculated by using FEM (Focus Exposure Matrix) for the simulated contours of resist
patterns. This flow is repeated. The lithography margin with this flow is compared with that of actual exposed
wafers. Repeatability and reliability of the lithography margin is evaluated. As a result, accuracy of the photomask
pattern contour extraction tool is discussed.
We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM . The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account.
Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.