In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.
We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.
Electron Projection Lithography (EPL) provides a fundamental advantage in resolution. In this paper, resolution improvement of EPL masks and minimum resolution in EPL exposure are addressed. In order to improve the mask resolution, we applied membranes thinner than typical thickness of 2 um to e-beam scattering layers of the EPL stencil masks. Although strength of the membrane generally deteriorates with decrease in the membrane thickness, the EPL masks having 1-um-thick scattering layers were feasibly fabricated. Reduction of the membrane thickness down to 1 um considerably improved the mask minimum feature size to resolve 120-nm holes and 80-nm lines which corresponded to 30 nm and 20 nm on wafer dimension, respectively, in the 4x demagnification EPL exposure system. The application of the 1-um-thick membrane simultaneously brought the high resolution and good pattern qualities: CD uniformity less than 10 nm in 3σ with pattern sidewall angle range of 90° ± 0.2°. We performed wafer exposure experiments in combination of the EPL exposure tool NSR-EB1A (Nikon) and the 1-um-thick membrane mask, and obtained the resolution performance of 40-nm holes on the wafer. We conclude that the application of the 1-um-thick membrane to the e-beam CD qualities. The exposure resolution of 40-nm holes on the wafer reveals the EPL exposure system to be a potential solution for contact layers in the future technology node.
Electron Projection Lithography (EPL) has been identified as a viable candidate of the next-generation lithography technologies for the sub-65-nm nodes. The development of a low-distortion mask is essential for meeting the stringent requirements at these lower nodes. This research focused on predicting the influence of mask fabrication and pattern transfer on the image placement (IP) accuracy of a 200-mm EPL mask. In order to quantify the in-plane distortions of the freestanding membranes, three-dimensional finite element (FE) models (full mask and submodels) have been developed.
A typical process flow including thin-film deposition, pattern transfer, and tool chucking was simulated with the FE models. Full mask models were used to characterize the global response of the mask, whereas submodels of the individual membranes provided details of the localized distortions on a subfield-by-subfield basis. In addition, local (subfield) correction schemes were replicated in the FE simulations. A parametric study was conducted to identify critical variables in the mask fabrication process. Pattern transfer was modeled using appropriate equivalent modeling techniques. IP errors of membranes with patterned areas of 4 mm × 4 mm and 1 mm × 1 mm were compared in the current study, illustrating the advantages / disadvantages of the two formats. The numerical models developed here have been used to investigate the proposed EPL mask formats, as well as the materials, fabrication processes, and general system parameters required to achieve the necessary pattern placement accuracy.
Electron projection lithography (EPL) has high-resolution capability of meeting the 45-nm technology node, especially for the “hole” process. A first-generation EPL has been developed and improved at Nikon and Selete. Defect free mask is indispensable for successful introduction of this technology into the production stage. However, an EPL mask is considerably different from today's optical photomask, especially due to its 3-D structure. Hence the conventional methods of quality assurance used for optical photomask are not applicable for EPL mask. Selete is now developing a series of defect inspection and repair systems for an EPL stencil mask infrastructure. In our previous work we verified a number of defect inspection and repair systems through a sequential process. We confirmed good sensitivity for ”hole” inspection, and accuracy of consistent template repair method through the various hole-defect types. Based on our previous work, here in this work we focus on Gas Assisted Etching (GAE) because the majority of the defects are black type defects in smaller features, especially at 45-nm node. The motivation here is to investigate on GAE repair for real usage at 45-nm node. In this paper we verified the capability of repair technology for isolated holes including smaller features. Moreover, we confirmed that the problems encountered in dense hole forming can be resolved.
Electron projection lithography (EPL) is one of the most promising candidates for the next generation lithography toward the hp 45 nm-node and beyond. EPL employs a stencil mask made from 200 mm Si wafer without a support frame, therefore chucking of an EPL tool and a metrology tool causes deformation in an EPL reticle. However, linear components of sub-field (SF) position error can be corrected by reticle alignment features of an EPL tool, whereas the non-linear components of SF position error can be corrected where each SF is measured beforehand and the corresponding reticle distortion correction (RDC) data is fed into the EPL exposure tool. In order to realize higher throughput, expanding SF to 4 mm-sq on reticle scale from the present 1 mm-sq is examined at the future EPL tool. For our studies we have investigated global image placement (IP), local IP, and pattern distortion of two kinds of EPL reticle. Currently we find the effect of mask IP on wafer scale is less than 9 nm, and we believe that in the near future the EPL mask IP target for the hp 45 nm-node could be realized for both of SF size.
Electron projection lithography (EPL) is one of the most promising candidates for the next generation lithography toward the hp 45 nm-node and beyond. EPL employs a stencil mask made from 200 mm Si wafer without a support frame, therefore chucking of an EPL tool and a metrology tool causes deformation in an EPL reticle. However, linear components of sub-field (SF) position error can be corrected by reticle alignment features of an EPL tool, whereas the non-linear components of SF position error can be corrected where each SF is measured beforehand and the corresponding reticle distortion correction (RDC) data is fed into the EPL exposure tool. The SF position error can be viewed as inter-SF IP error where it can be affected by the repeatability of measurement and by the repeatability of distortions caused by the chucking of the measurement tool and the EPL tool. The other part of inter-SF IP comes from the residual that relates to global IP. Besides inter-SF IP, intra-SF IP can be divided into "local IP" and "pattern distribution". For our studies we have investigated the measurement repeatability of the metrology tool (Nikon XY-6i), distortion repeatabilities caused by the chucking of the metrology tool and the EPL tool (NSR-EB1A), global and local IPs, and pattern distortion. Currently we find the effect of mask IP on wafer scale is less than 9 nm, and we believe that in the near future the EPL mask IP target for the hp 45 nm-node could be realized.
Electron projection lithography (EPL) has high-resolution capability of meeting the 65 nm technology node and beyond. A first-generation EPL has been developed and improved at Nikon and Selete. Defect free mask is indispensable for successful introduction of this technology into the production stage. However, an EPL mask is considerably different from today's optical photomask, especially due to its 3-D structure. Hence the conventional methods of quality assurance used for optical photomask are not applicable for EPL mask. Selete is now developing a series of defect inspection and repair systems for an EPL stencil mask infrastructure. In our previous work we reported on the individual systems for defect inspection and mask repair by using programmed defects. Moreover, we verified a number of the defect inspection and repair systems through a sequential process. In this work the motivation is to investigate relationship issues among these tools for future applications, such as defect printability, CD controllability, calibration, optimization, performance matching, and automated operation.
Proc. SPIE. 5751, Emerging Lithographic Technologies IX
KEYWORDS: Metals, Transmission electron microscopy, Lithography, Scanners, Copper, Scanning electron microscopy, Resistance, Electron beam lithography, Overlay metrology, Chemical mechanical planarization
We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.
Selete is developing a series of defect inspection and repair systems for electron projection lithography (EPL) stencil mask infrastructure, that includes tools and software development, and also verification by EPL exposure systems. The work is carried out in collaboration with Dai Nippon Printing, Toppan Printing and HOYA. A
system for defect inspection of EPL stencil mask is developed with TOKYO SEIMITSU and HOLON. Another system for defect repairs is developed with SII NanoTechnology. The performances of these systems need to be verified for their further improvement and optimization. In this paper, we verified a series of defect inspection and
repair systems through a sequential process. We can say that EPL mask infrastructure is established and our work has
made significant contribution to it.
Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.
An optical module is assembled using a passive-alignment technique. A laser diode (LD), a single mode fiber with a ferrule and a monitor photo diode (PD) are mounted on a silicon (Si) substrate. The LD and the PD are adjusted in three axis direction (horizontal axis, light axis and horizontal angle axis) to be die-bonded. The fiber is laid between a V-groove on the Si substrate and a glass block. In the perpendicular axis direction, the V-groove width is set so that the LD active layer and the fiber core are at the same height. The optical devices and the fiber facet are sealed using a thermosetting resin material. The Si substrate is bonded in a nonhermetic-sealed plastic package. The coupling losses of the LDs to the butt-jointed single mode fibers are estimated to be 7.4 to 10.8 dB, to the average value of 8.6 dB. The tracing errors of the fabricated modules are less than +/- 1.5 dB at ambient temperature from -40 to +85 degrees centigrade. The coupling losses change at the damp-heat stress test (85 degrees and 85% RH) is less than +/- 0.5 dB after more than 5,000 hours.