Nanoimprint lithography (NIL) is regarded as one of the candidates for next generation lithography toward singlenanometer manufacturing. Among the wide variety of imprint methods, Jet and Flash Imprint Lithography (J-FIL) process is the most suitable for IC manufacturing for which high productivity and high precision is required. Unlike spin-coating-based NIL process J-FIL process has some capabilities to solve the issue by controlling local resist volume based on pattern design of the patterned mask (template). In order to improve NIL process, in this paper we focus on understanding the occurrence of non-filling defects during resist filling into the template features, and propose the new optimization concept of drop amount and drop arrangement for fast filling and defect reduction.
Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. Layout and process dependent hotspots become a significant issue for application in smaller pattern size device and, design for manufacturing (DFM) flow comprising imprint process has to be prepared. Focusing on resist drop arrangement method as a process margin expansion knob, simulated non-fill defect is compared with experimental result. Finally, drop arrangement-related hot-spot extraction/modification flow utilizing total NIL simulation is proposed.
Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed
In principal, the critical dimension (CD) of Nanoimprint lithography (NIL) pattern is determined by the CD of the template pattern. Unless one template is changed to another, NIL does not have a knob for direct control of the CD, such as the exposure dose and focus in optical lithography. Alternatively, the CD would be controlled by adjusting the thickness of the residual layer underneath the NIL pattern and controlling the etching process to transfer the pattern to a substrate. Controlling the residual layer thickness (RLT) can change the etching bias, resulting in the control of the CD of etched pattern. RLT is controllable by the resist dispense condition of the inkjet. For CD control, the metrology of RLT and feedback of the results to the dispense condition are extremely important. Scatterometry is the most promising metrology for the task because it is nondestructive 3D metrology with high throughput. In this paper, we discuss how to control CD in the NIL process and propose a process control flow based on scatterometry.