The potentiality of line width roughness (LWR) reduction by ion implantation (I/I) in the extreme ultra violet (EUV)
lithography resist pattern was studied. The Argon ions were implanted to the Line-and-Space (L/S) pattern of EUV resist
with changing ion energy, dose and incident angle. The LWR and line width of 32 nm half-pitch L/S pattern was
evaluated after development, after I/I and after dry etching of the experimental thin hard mask beneath the resist pattern.
The LWR of 4.2 nm 3 σ, corresponding to the reduction of 1.6 nm, was obtained for resist after I/I with relatively low
energy condition of 1~5 keV. On the other hand, the best value of LWR after hard mask dry etching was 3.6 nm 3σ with I/I energy of 15 keV. It was found that preferable I/I condition for LWR reduction cannot be decided I/I alone but
should be optimized combined with etching.
Extreme ultraviolet (EUV) lithography is a promising candidate for 2x-nm-node device manufacturing. Management of effective dose is important to meet the stringent requirements for critical dimension control. As a test pattern for a lithography tool evaluation, the effective dose monitor (EDM) demonstrates sound performance in dose monitoring for optical lithography, such as KrF lithography. The EDM can measure an exposure dose with no influence on defocus, because the image of an EDM pattern is produced by the zeroth-order ray in diffraction only. When this technique is applied to EUV lithography, the mask shadowing effect should be taken into consideration. We calculated the shadowing effect as a function of field position and applied it to correction of the experimental dose variation. We estimated the dose variation in EUV exposure field to be 2.55% when corrected by the shadowing effect. We showed that the EDM is useful for EUV lithography.
EUV lithography is a promising candidate for 2x-nm-node device manufacturing. Management of effective dose is
important to meet the stringent requirements for CD control. Test pattern for a lithography tool evaluation, the effective
dose monitor (EDM), shows good performance in the dose monitoring for optical lithography, for example, KrF
lithography. The EDM can measure an exposure dose with no influence on defocus, because the image of an EDM
pattern is produced by the zero-th-order ray in diffraction only. When this technique is applied to EUV lithography, the
mask shadowing effect should be taken into consideration. We calculated the shadowing effect as a function of field
position and applied it to correction of the experimental dose variation. We estimated the dose variation in EUV
exposure field to be 2.55 % when corrected by the shadowing effect. We showed that the EDM is useful for EUV
We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm
technology node by integrating it into standard semiconductor process flows because we believe that device integration
exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In
this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and
first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art
defectivity (~0.3 defects/cm<sup>2</sup>). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably
higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV
lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the
0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.
We reported that we were successful in our 45nm technology node device demonstration in February 2008 and 22nm
node technology node device patterning in February 2009 using ASML's Alpha Demo Tool (ADT).1, 2, 3 In order to
insert extreme ultraviolet (EUV) lithography at the 15nm technology node and beyond, we have thoroughly
characterized one EUV mask, a so-called NOVACD mask.
In this paper, we report on three topics. The first topic is an analysis of line edge roughness (LER) using a mask
Scanning Electron Microscope (SEM), an Atomic Force Microscope (AFM) and the Actinic Inspection Tool (AIT) to
compare resist images printed with the ASML ADT. The results of the analysis show a good correlation between the
mask AFM and the mask SEM measurements. However, the resist printing results for the isolated space patterns are
slightly different. The cause of this discrepancy may be resist blur, image log slope and SEM image quality and so on.
The second topic is an analysis of mask topography using an AFM and relative reflectivity of mirror and absorber
surface using the AIT. The AFM data show 6 and 7 angstrom rms roughness for mirror and absorber, respectively. The
reflectivity measurements show that the mirror reflects EUV light about 20 times higher than absorber.
The last topic is an analysis of a 32nm technology node SRAM cell which includes a comparison of mask SEM image,
AIT image, resist image and simulation results. The ADT images of the SRAM pattern were of high quality even though
the mask patters were not corrected for OPC or any EUV-specific effects. Image simulation results were in good
agreement with the printing results.
We describe progress in implementation of blur-based resolution metrics for EUV photoresists. Three sets of blur
metrics were evaluated as exposure-tool independent comparison methods using the Sematech-LBNL EUV microexposure
tool (MET) and ASML α-Demo Tool (ADT) full-field EUV scanner. For the two EUV resists studied here,
deprotection blurs of 15 nm are consistently measured using blur estimation methods based on corner rounding, contact
hole exposure latitude, and process window fitting using chemical amplification lumped parameter models. Agreement
between methods and exposure tools appears excellent. For both resists, SRAM-type lithographic diagnostic patterns at
80 nm pitch are only modestly sensitive to OPC blur compensation and display robust printability (RELS ~ ILS near 50
μm<sup>-1</sup> for multiple trench geometries) on the ASML ADT. These findings confirm the continuing utility of blur-based
metrics in a) guiding resist selection for use in EUV process development and integration at the 22 nm logic node and
below, and b) providing an exposure-tool independent set of metrics for assessing progress in EUV resist development.
The performance of a 0.25NA full-field EUV exposure tool is characterized in terms of CD uniformity, focus
and overlay control, as well as dose uniformity. In addition to the characterization of the scanner, we explore the use of
scatterometry techniques for the measurements of extremely fine resolution features, with critical dimensions below 40
nm. The stability of the scanner performance over an extended period of time is assessed.
Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the
wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and
serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie
and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a
KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding
detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to
assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous
study  were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and
discussed together with a defect classification.
Various issues related to non-telecentric mask effects for EUV lithography will be discussed in this paper. First, a raytracing
approach will provide a conceptual description as to the nature of non-telecentric thick mask effects, highlighting
the behavior of various edge types and corners. Rigorous modeling of these effects are discussed along with a few
consequences of improper modeling. A series of simulation and experimental studies are presented to probe both the
one- and two-dimensional impact of thick mask effects. It will be shown that a simple constant edge bias appears
sufficient for 1D features, but begins to break down when space-widths are less than about 45 nm. Investigation into the
impact of corners and small 2D features indicates that a simple edge-based bias also breaks down for edge lengths less
than about 60nm. A sample set of rules-based post-OPC HV corrections for 22nm node dimensions are proposed,
although based on experimental results, it is concluded that more accurate resist modeling and scanner stability are
required before being able to precisely predict and control HV effects. Finally, with some simplifying assumptions,
simulation is used to predict the extent of potential HV effects of future EUV imaging systems.
The EUV exposure tool settings and OPC strategies to be used for the 16 nm logic node are discussed. Imaging
simulation was done for various types of CD through pitch patterns to investigate the tradeoff between NA, illumination
settings, and resist diffusion blur. EUV optics still provides very good optical resolution at 56 nm min pitch, but resist
diffusion degrades imaging contrast significantly. The CD variations due to resist blur are relatively larger for EUV
lithography than they are for 193 nm lithography, because of the high quality of the EUV lithography images. EUV
shadowing effect and flare effect contribute additional CD variations, which need to be corrected and controlled.
Nonetheless, a resist blur of about 15 nm FWHM or better provides adequate imaging performance even with current
EUV optical settings of 0.25 NA and conventional illumination for 28 nm half-pitch applications. Experimental results
show that state-of-art EUV resists have resist blur values close to this requirement, although their current performance is
limited by resist material properties and processing conditions.
EUV lithography is one of the most promising methods for next-generation lithography below 22 nm half pitch.
However, critical issues such as availability of a clean powerful source, resist resolution and sensitivity, and defect-free
masks have yet to be overcome.
Flare is one of the key issues for EUV lithography critical dimension (CD) control.<sup>1</sup> The cause of flare is scattered light
due to the surface roughness of the mirrors in the projection optics. Mirror surface control techniques have reached the
angstrom level and are approaching physical limits.
Therefore, it is important to understand and evaluate "actual" flare and begin developing a mitigation strategy.
In this paper, we report on two evaluations of short-range flare using the ASML Alpha Demo Tool (ADT) in Albany,
NY.<sup>2</sup> First, a series of donut shaped patterns of varying size are evaluated in order to determine the impact of flare on the
imaging of a central post surrounded by a clear annulus. A spillover parameter is used to estimate the ADT flare point
spread function. The results, which show roughly a slope of -1 on a log-log plot, are in agreement with those expected
from the power spectral density (PSD) due to mirror surface roughness. Second, an investigation into out-of-band (OoB)
radiation was performed, which leverages OoB reflection from the ADT's reticle masking (REMA) blades. We estimate
that the amount of OoB radiation is on the order of 3 to 4 percent of the EUV light.
On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and
below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.
In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography;
the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV
mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of
mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV
lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The
CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured
overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided
ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first
interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.
The patterned integration wafers have been processed through metal deposition and polish at the contact level and are
now being patterned at the first interconnect level.
We have used ASML's full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an
Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks.
The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV
reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at
naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also
integrated into a standard process flow where the other layers were patterned using more conventional 193-nm
This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the
28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect
populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both
conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find
good correlations between reticle level defects and the resulting wafer exposure defects.
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm<sup>2</sup>, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
Proc. SPIE. 6151, Emerging Lithographic Technologies X
KEYWORDS: Electron beams, Amplifiers, Control systems, Photomasks, Beam shaping, Optical alignment, Data conversion, Electron beam direct write lithography, Semiconducting wafers, Vestigial sideband modulation
A character projection (CP)-type, low energy, electron beam direct writing (EBDW) system, for quick-turn-around-time and mask-less device fabrications of small production lots featuring a variety of designs has been developed. This system, named the EBIS (Electron Beam Integrated System), can satisfy a set of requirements for EBDWs, including higher throughput and mask-less exposure. A standardized CP aperture method that enables reduction in the number of EB shots without frequent aperture making has been applied as a means for attaining effective CP and mask-less fabrication. This breakthrough was able to be realized only by using low energy EB with the advantage of the free proximity effect. To resolve critical low energy EB issues, a compact EB column, equipped with monolithic deflectors and lenses for restricting beam blur caused by Coulomb interaction, was developed and put to use. Sufficient resolution, corresponding to 100 nm L/S patterns, was attained by using a thin-layered resist process. As the mark detection method, voltage contrast imaging using a micro channel plate was used. This method made it possible to detect buried marks when using low energy EB. The authors are currently verifying the basic performance of this EBIS. This paper outlines and discusses geometrical details and performance data of this system.