As the critical dimension keeps shrinking, mask topography effect (Mask3D) becomes considerable to impact the lithography modeling accuracy and the quality of full-chip OPC. Among many challenges in Mask3D modeling, it is critical and particularly demanding to treat off-axis illumination (OAI) properly. In this paper, we present a novel Mask3D model that is completely test pattern- and optics- independent. Such model property enables greatly improved performance in terms of accuracy and consistency on various pattern types (1D/2D) and through a wide range of focus conditions, while no runtime overhead is incurred. The novel model and formulation will be able to save significant modeling time and greatly improve the model reliability, predictability and ease of use. Experimental results validate the claims and demonstrate the superiority to the current state-of-the-art Mask3D modeling method. This is a new generation Mask3D modeling process.
As we advances into 14/10nm technology node, single patterning technology is far from enough to fabricate the
features with shrinking feature size. According to International Technology Roadmap for Semiconductors in
2011,<sup>1 </sup>double patterning lithography is already available for massive productions in industry for sub-32nm half
pitch technology node. For 14/10nm technology node, double patterning begins to show its limitations as it uses
too many stitches to resolve the native coloring conflicts. Stitches will increase the manufacturing cost, lead
to potential functional errors of the chip, and cause the yield lost. Triple patterning lithography and E-Beam
lithography are two emerging techniques to beat the diffraction limit for current optical lithography system. In
this paper, we investigate combining the merits of triple patterning lithography and E-Beam lithography for
standard cell based designs. We devise an approach to compute a stitch free decomposition with the optimal
number of E-Beam shots for row structure layout. The approach is expected to highlight the necessity and
advantages of using hybrid lithography for advanced technology node.
With the minimum feature size keeps shrinking, there are increasing difficulties to print these small features using one exposure (LE) or double exposures (LELE). To resolve the inherent physical limitations for current lithography techniques, triple patterning lithography (LELELE) has been widely recognized as one the most promising options for 14/10nm technology node. For triple patterning lithography (TPL), the designers are more interested in finding a decomposition with none of the three masks overwhelms the other. This color balancing issue is of crucial importance to ensure that consistent and reliable printing qualities can be achieved. In our previous work,18 a simple color balancing scheme is proposed to handle designed without stitches, which is not capable of handling complex designs with stitches. In this paper, we further extend the previous approach to be able to simultaneously optimizing the number of stitches and balancing the color usage in the three masks. This new approach is very efficient and robust, and guarantees to find a color balancing decomposition while achieving the optimal number of stitches. For the largest benchmark with over 10 million features, experimental results show that the new approach achieves almost perfect color balancing with reasonable runtime.
Mask topography (Mask3D) effect is one of the most influential factors in sub-28 nm technology node. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. In the meanwhile, Mask3D modeling must be able to handle the off-axis illumination (OAI) condition accurately. In this paper, we propose our full chip Mask3D modeling method which is an extension to the edge-based Mask3D model. In our modeling flow, we first review the edge-based Mask3D model and then analyze the impact from the off-axis source. We propose a parameter-based extension to characterize the off-axis impact efficiently. We further introduce two methods to calibrate the OAI-aware parameters by using rigorous or wafer data as the reference. Our experimental results show the great calibration accuracy throughout the defocus range with OAI sources, and validate the accuracy of our two parameter calibration approach.
As the technology node keeps shrinking down to sub-28 nm, mask topography (Mask3D) effect is one of the most influential factors to draw intensive research lately. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. Different approaches have been tried to resolve the difficulties in the full-chip modeling, but so far none of the existing Mask3D modeling methods have succeeded in meeting all the three criterion at the same time. It is often seen that an existing Mask3D model to succeed in one or two criteria, but fails in the rest. In this paper, we propose our innovative full chip Mask3D modeling method to successfully handle the above criterion at the same time. To our best of knowledge, it is the first ever Mask3D modeling in literature that is be able to achieve this goal. In our modeling flow, we first analyze the Mask3D effect by using rigorous simulation as the reference and generate edge-based kernels to mimic the Mask3D effect near the feature boundaries. The flexibility of handling the kernel helps us enable the support for all-angle patterns and be extendable for edge coupling effect and off-axis illumination. Our experimental results show that with only less than 30% runtime overhead compared to the conventional Mask2D model, we are able to achieve less than 0.8 nm CD RMS on the flexible feature patterns. An ILT-based OPC and simulation result is provided to validate the capability of all-angle support of our proposed model.
Directed self-assembly (DSA) technology has already demonstrated its capability for isolated and grouped contact/via pattern for 1D gridded design. If we reverse the resist tune, this technique can also be used to implement the cut printing. However, for this purpose, we need to redistribe the cuts by extending the real wires to form the desired cut distribution for template mask making. Based on this assumption, we propose an algorithm to redistribute the original cuts such that they form groups of non-conflict DSA templates. Experimental results demonstrate that our method can effectively redistribute the cuts and improve the layout manufacturability.
As the current 193nm ArF immersion lithography technology is approaching its bottleneck, multiple patterning techniques have to be introduced to fulfill the process requirements in the sub-20nm technology node. Among all different patterning techniques, triple patterning lithography (TPL) is one of the major options for 14 nm or 10 nm technology node, which has a substantial requirement on process control and cost control at the same time. Patterning decomposition is the key step for the success of TPL. In the conventional TPL lithography, a constant spacing distance <i>d<sub>min</sub></i> is used to determine whether two nearby features should be on the same mask. However, in reality, the no-print and the best-print scenarios can never be separated by a clear constant number. Indeed, the decomposition criteria is closed related to lithography printing parameters, pattern types, and geometry distances. The conventional spacing rule with a constant number is way too simple. In this paper, we re-evaluate the conventional minimum spacing rule and utilize a local pattern cost model to evaluate our previous optimal TPL algorithm. Given a user specified local pattern aware cost model, our algorithm can easily embed the model into our formulation and compute an optimal solution. This demonstrates the extendability and robustness of our previous TPL algorithm.
Extreme ultraviolet lithography (EUVL) is a leading candidate for next generation lithography (NGL). At 11nm technology node, the size of the minimum printable multi-layer (ML) mask defect is as small as 20nm. As a result, it is extremely difficult to produce defect-free ML mask blanks. Instead, by allowing a certain number of printable defects on the blank, the EUVL cost of ownership can be tremendously reduced. However, those printable blank defects must be mitigated later in the mask fabrication process in order not to sacrifice yield. One effective defect mitigation approach is to cover the defects by device patterns, such that the defects will no longer be printable. However, there can be billions of device patterns in one single layer which have to be shifted together within a certain margin due to the exposure alignment requirement. Thus an efficient way to cover all defects simultaneously via global device pattern shifting is sorely needed. In addition, it is very difficult to measure the position of each defect accurately with the current blank inspection tool, so the defect position inaccuracy has to be taken into consideration at the same time. This paper formulates the blank defect coverage problem into a rectilinear polygon shrinking and intersection problem and develops a highly efficient algorithm whose time complexity is linear with respect to the density of device patterns. In addition, within the shift margin there are usually multiple positions to locate a layout on a defective blank where all defects are simultaneously covered by the device patterns; our algorithm is able to report the optimal layout location with the maximum tolerance for the inspection inaccuracy.
Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary
before mass production. One effective way to mitigate the defect impact is to increase the distance between the
defects and feature boundaries such that the defects will not affect the printing of the features. Some algorithms
have been developed to move the whole layout within the exposure field in order to avoid all defect impact.
However, in reality the die size is usually much smaller than the exposure field, such that one blank is packed
with multiple copies of the die, and each die can be placed independently within the exposure field. In this
paper, we develop an EUV reticle placement algorithm to maximize the number of valid dies that are immune
to defects. Given the layout of a die and a defective blank, we first apply a layout relocation algorithm to find
all feasible regions for the die on the blank. Then we develop an efficient placement algorithm to place the dies
within the feasible regions one at a time until all feasible regions are fully occupied. The simulation results show
that our algorithm is able to find a solution efficiently and the number of valid dies placed by our algorithm is
very close to the optimal solution.
Self-aligned quadruple patterning (SAQP) lithography is one of the major techniques for the future process
requirement after 16nm/14nm technology node. In this paper, based on the existing knowledge of current 193nm
lithography and process flow of SAQP, we will process an early study on the definition of SAQP-friendly layout.
With the exploration of the feasible feature regions and possible combinations of adjacent features, we will define
several simple but important geometry rules to help define the SAQP-friendliness. Then, we will introduce a
conflicting graph algorithm to generate the feature region assignment for SAQP decomposition. Our experimental
results validate our SAQP-friendly layout definition, and basic circuit building blocks in the low level metal layer
Self-aligned double patterning (SADP) lithography is a novel lithography technology which has the capability to
define critical dimension (CD) using one single exposure, therefore holding a great opportunity for the next generation
lithography process for the overlay mitigation. However, a necessary design manufacturing co-optimization
step - the non-decomposability position detection (hot spot detection) - is still immature. In this paper, targeting
the hot spot detection difficulties in SADP process, we first revisit out previous ILP-based SADP decomposition
algorithm and provide an extended ILP-based hot spot detection without any preconditions on the design. Then,
with some simple requirement that is commonly seen in 2D random layout, we further provided a graph based
hot spot detection for an efficient hot spot detection. From the Nangate standard cell library, our experiment
validates the hot spot detection process and demonstrates an SADP friendly design tyle is necessary for the
upcoming 14nm technology node.
Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary
before mass production. Currently almost all the defect mitigation methods are focused on mitigating the defect
impact of one blank on one design. However, since the EUV mask vendors always have multiple designs and blanks
in hand, it is also very important to consider all designs and blanks together to mitigate the total defect impact.
This paper proposes a new EUV mask preparation strategy which optimally matches a set of defective blanks
with multiple designs to mitigate the total defect impact. In the first step, an efficient layout relocation algorithm
is adopted to minimize the defect impact of each blank on each design. Then, depending on whether blank defects
are allowed to be compensated, we formulate the two different types of design-blank matching problems as flow
problems and solve them optimally. Compared to sequential matching, the proposed simultaneous matching
strategy shows advantages in both blank utilization and defect compensation cost minimization.
In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research
work on 2-D cell characterization shows that the timing variations can be characterized by the timing model.
However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its
advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more
accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents
a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform
lithography simulation on the poly gate array generated by dense line printing technology, which constructs the
poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that,
circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay
and power distribution curves are generated, which accurately predict the circuit performance of standard cells.
In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing
perspectives, which shows great advantages in accurate circuit analysis and yield improving.
Self-aligned double patterning (SADP) lithography is a novel lithography technology that has the intrinsic
capability to reduce the overlay in the double patterning lithography (DPL). Although SADP is the critical
technology to solve the lithography difficulties in sub-32nm 2D design, the questions - how to decompose a
layout with reasonable overlay and how to perform a decomposability check - are still two open problems
with no published work. In this paper, by formulating the problem into a SAT formation, we can answer the
above two questions optimally. This is the first published paper with detailed algorithm to perform the SADP
decomposition. In a layout, we can efficiently check whether a layout is decomposable. For a decomposable layout,
our algorithm guarantees to find a decomposition solution with reasonable overlay reduction requirement. With
little changes on the clauses in the SAT formula, we can address the decomposition problem for both the positive
tone process and the negative tone process. Experimental results validate our method, and decomposition results
for Nangate Open Cell Library and larger test cases are also provided with competitive run times.
When the VLSI technology scales down to sub 40nm process node, the application of EUV is still far from
reality, which forces 193nm ArF light source to be used at 32nm/22nm node. This large gap causes severe light
refraction and hence reliable printing becomes a huge challenge. Various resolution enhancement technologies
(RETs) have been introduced in order to solve this manufacturability problem, but facing the continuously
shrinking VLSI feature size, RETs will not be able to conquer the difficulties by themselves. Since layout
patterns also have a strong relationship with their own printability, therefore litho-friendly design methodology
with process concern becomes necessary. In the very near future, double patterning technology (DPT) will be
needed in the 32nm/22nm node, and this new process will bring major change to the circuit design phases for
In this paper, we try to solve the printability problem at the cell design level. Instead of the conventional 2-D
structure of the standard cell, we analyze the trend of the application of 1-D cell based on three emerging double
patterning technologies. Focusing on the dense line printing technology with off-axis illumination, line-end gap
distribution is studied to guide our methodology for optimal cell design.
As the VLSI technology scales into deep submicron nodes, Double Patterning Technology (DPT) has shown its necessity
for the under 45nm processes. However, the litho-related and process-related issues, such as the overlay control for CD
uniformity, decomposition, feature stitching technology and some other problems make up the main challenges for the
implementation of DPT. Due to Optical Proximity Correction (OPC), the complexity and data volume of DPT increase
dramatically, which severely increase the application cost and create manufacturability problems.
In this paper, we mainly talk about the interactions between DPT and OPC and propose a new Model-Based OPC
methods for the decomposition in DPT procedures. To address the printing problems with cutting sites for feature split,
we introduce an overlap correction method on the stitching locations. For any re-cut and/or redesigned pattern after
verification, we categorize DP decompositions and introduce a new Adaptable OPC (Ad-OPC) algorithm by reusing post
OPC layout to speed up the correction and improve its convergence according to environment surrounding. The method
can be easily incorporated into existing MB-OPC framework. To test this method, total Edge Placement Error (EPE) and
runtime are calculated in our experiments. Results show that over 90% runtime can be saved compared with
conventional OPC procedure. It increases the robustness and friendliness of pattern correction as well as stitches features
Disconnection between design and manufacturing has become a prevalent issue in modern VLSI processes. As
manufacturability becomes a major concern, uncertainties from process variation and complicated rules have increased
the design cost exponentially. Numerous design methodologies for manufacturability have been proposed to improve
the yield. In deep submicron designs, optical proximity correction (OPC) and fill insertion have become indispensable
for chip fabrication. In this paper, we propose a novel method to use these manufacturing techniques to optimize the
design. We can effectively implement non-uniform wire sizing and achieve substantial performance and power
improvement with very low costs on both design and manufacturing sides. The proposed method can reduce up to 42%
power consumption without any delay penalty. It brings minor changes to the current design flow and no extra cost for
SOFT (Smooth OPC Fixing Technique) is a new OPC flow developed from the basic OPC framework. It provides a new
method to reduce the computation cost and complexities of ECO-OPC (Engineering Change Order - Optical Proximity
Correction). In this paper, we introduce polygon comparison to extract the necessary but possibly lost fragmentation and
offset information of previous post-OPC layout. By reusing these data, we can start the modification on each segment
from a more accurate initial offset. In addition, the fragmentation method in the boundary of the patch in the previous
OPC process is therefore available for engineers to stitch the regional ECO-OPC result back to the whole post-OPC
layout seamlessly. For the ripple effect in the OPC, by comparing each segment's movement in each loop, we much free
the fixing speed from the limitation of patch size. We handle layout remodification, especially in three basic kinds of
ECO-OPC processes, while maintaining other design closure. Our experimental results show that, by utilizing the
previous post-OPC layout, full-chip ECO-OPC can realize an over 5X acceleration and the regional ECO-OPC result can
also be stitched back into the whole layout seamlessly with the ripple effect of the lithography interaction.