HgCdTe has been shown to be the first semiconductor exhibiting single-carrier multiplication in avalanche photodiodes (APDs) up to gain values larger than 1000 and with close to zero excess noise. These results have opened a new windows for low-flux and versatile imaging. In this paper, we report the latest results on MWIR HgCdTe APDs manufactured at SITP. These APDs display a gain of 1000 around 10V reverse bias. The excess noise factor is between 1.2 to 1.45 up to gain of 100, and the quantum efficiency is more than 60% from 1μm wavelength to peak wavelength 4.2 μm. These results show that the technological processes used at SITP are well adapted to APD manufacturing. However, at present, the dark current starts increasing significantly faster than the gain at high bias, and then the device becomes dark current noise limited. APD gain performance was successfully modeled by the simulation of electrical characteristics used Synopsys Sentaurus based on Okuto-Crowell ionizaition coefficient model. Therefore, Sentaurus would be used as a powerful predictive tool for SITP technology and stress its reproducibility and optimize the devices .
This paper reports the development of 2000×256 format SWIR HgCdTe/Si FPA with multiple-choice gain (i.e. multiple-choice charge handling capacity) for hyperspectral detection. The spectral resolution is about 8nm. To meet the demands of variable low flux detection within each spectral band in the short wave infrared range, low dark current, low noise, variable conversion gains and high SNR (Signal to Noise Ratio) of FPA are needed. In this paper, we fabricate 512×512 pixel 30μm pitch SWIR HgCdTe diode array on Si by using a novel stress-release construction of HgCdTe chip on Si. Moreover, we design low noise, variable conversion gain and large dynamic range read-out integrated circuit (ROIC) and hybridized the ROIC on the HgCdTe diode array on Si substrate. There are 8-choice gains which can be selected locally according to the incident flux to meet high SNR detection demand. By high-accuracy splicing 4 512×512 HgCdTe/Si FPA we get mosaic 2000×512 FPA, and characterizations have been carried out and reveal that the array dark current densities on an order of 10<sup>-10</sup>A/cm<sup>2</sup>, quantum efficiency exceeding 70%, and the operability of 99.5% at operating temperature of around 110K. The SNR of this FPA achieved 120 when illuminated under 5×10<sup>4</sup>photons/pixel.
Proc. SPIE. 9674, AOPC 2015: Optical and Optoelectronic Sensing and Imaging Technology
KEYWORDS: Readout integrated circuits, Signal to noise ratio, Digital signal processing, Capacitors, Interference (communication), Capacitance, Signal processing, High dynamic range imaging, Analog electronics, Digital electronics
The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.
A 640×512 readout integrated circuit (ROIC) with 15um pixel pitch for middle-wave infrared focal plane arrays (MWIR FPAs) is designed in this paper. The 15um pixel pitch presents several challenges to the ROIC design, such as achieving the required charge storage capacity to preserve the high SNR and reading or processing the pixel signals correctly to achieve the required frame rate. A novel structure that four neighboring pixels share one integration capacitor is presented as a feasible approach to getting a large charge capacity in the limited pixel area. Meanwhile, the pixel circuit chooses the direct injection (DI) which occupies the small layout area as the input stage for MW and contains two sample and hold modules to further increase the charge capacity. Moreover,the peripheral analog signal chain circuit, which is composed of a PMOS source follower, a column amplifier and the complementary output stage, is designed to transfer the signals from unit cell with less voltage loss,lower power consumption, lower noise and higher linearity. More importantly, in our design, only half chain circuit are required therefore the corresponding power consumption will be reduced greatly. In order to accommodate this design, two kinds of pixel signal readout sequences are compared. By adopting the 0.18um 1P6M mixed signal CMOS process, the circuit architecture can make the effective charge capacity of 13Me- per pixel with 1.38V final output range. The 4×4 circuit layout will be fulfilled as a whole and in this way the effective integration capacitor can be increased. According to the simulation results, this circuit works well under 3.3V power supply and achieves 10MHZ readout rate and less than 0.1% nonlinearity.
Reliability is an important index to ensure the application of infrared focal plane arrays (IRFPAs) in complex environment, and it becomes a major bottleneck problem of IRFPAs’ development. Because of the characteristics such as type, nature, quantity, location and distribution et al, bad pixel which contains initial bad pixel and used bad pixel has outstanding advantage for failure analysis and reliability evaluation of IRFPAs. In this paper, the structure of IRPFAs has been introduced in detail, and the damage mechanisms of used bad pixel also have been analyzed deeply. At the same time, the feasibility to study IRPFAs' damage stress, failure position, damage mechanism has been discussed all around. The research of bad pixel can be used to optimize the structure and process, meanwhile it also can improve the accuracy of bad pixel identification and replacements.
Since the technology trend of the third generation IRFPA towards resolution enhancing has steadily progressed,the pixel pitch of IRFPA has been greatly reduced.A 640×512 readout integrated circuit(ROIC) of IRFPA with 15μm pixel pitch is presented in this paper.The 15μm pixel pitch ROIC design will face many challenges.As we all known,the integrating capacitor is a key performance parameter when considering pixel area,charge capacity and dynamic range,so we adopt the effective method of 2 by 2 pixels sharing an integrating capacitor to solve this problem.The input unit cell architecture will contain two paralleled sample and hold parts,which not only allow the FPA to be operated in full frame snapshot mode but also save relatively unit circuit area.Different applications need more matching input unit circuits. Because the dimension of 2×2 pixels is 30μm×30μm, an input stage based on direct injection (DI) which has medium injection ratio and small layout area is proved to be suitable for middle wave (MW) while BDI with three-transistor cascode amplifier for long wave(LW). By adopting the 0.35μm 2P4M mixed signal process, the circuit architecture can make the effective charge capacity of 7.8Me<sup>-</sup> per pixel with 2.2V output range for MW and 7.3 Me<sup>-</sup> per pixel with 2.6V output range for LW. According to the simulation results, this circuit works well under 5V power supply and achieves less than 0.1% nonlinearity.
An improved CMOS readout integrated circuit (ROIC) for N-on-P very long wavelength (VLWIR) detectors is designed, which has the ability to operate with a simple background suppression. It increases the integration time and the signal-to-noise ratio (SNR) of image data. A buffered gate modulation input (BGMI) cell as input circuit provides a low input resistance, high injection efficiency, and precise biasing voltage to the photodiode. By theoretically analyzing the characteristic parameters of MOS device at low temperature, a high gain’s feedback amplifier is devised which using a differential stage to provide the inverting gain to improve linearity and to provide tight control of the detector bias. The final chip is fabricated with HHNEC 0.35um 1P4M process technology. The measurement results of the fabricated readout chip under 50K have successfully verified both readout function and performance improvement. With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V. At the same time, the total power dissipation is less than 200mW, and the maximum readout speed is more than 2.5MHz.
Infrared focal plane HgCdTe device is used in the environment of complicated astrospace radiation. To achieve the instrument’s actual service life, the anti-radiation ability is needed to study in our research. The irradiation-induced invalidation mechanism of semiconductor materials is introduced in this paper, and the screening experiments' total radiation dose of American Military Standard is also investigated in our study. Through the simulation of astrospace radiation effect by <i>γ</i> -irradiation, the experimental procedures are proved to be rational by the analysis of the experimental data. With the domestic conditions, radiation screening procedures which meets the practical need is suggested.
Design of readout-integrated circuit(ROIC) with high frequency and low signal for 512×256 short wavelength(SW) inferred-focal-plane-arrays(IRFPAs) is presented. The ROIC with high performance in frame rate can integrate and read out the low signal. An analog signal chain, which contains CTIA, CDS module, amplifier of charge and complementary output stage, can satisfy the high frequency and low signal application. A reliable digital control structure of IRFPA ROIC is presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than regular lines, can be selected to readout. The simulation and verification are completed both before and after completing the layout. The circuit’s structure and operation principle are analyzed under the environment of mix-signal, and the result shows that the output dynamic range is over 2.5V, the charge capacity is more than 1Me-, the frame rate is 250Hz, the linearity within useful dynamic range is above 99.9 percent.
A readout integrated circuit (ROIC) for 320× 256 middle-wave and long-wave infrared focal plane arrays, is studied in this paper. This circuit operates in integrating-while-reading (IWR) mode with the frame rate higher than 100fps. A novel DI structure is used for signal acquisition of middle wave while BDI structure for long wave. It is common that trade-offs always exist between chip area and performances in integrated circuits design. In order to get high injection efficiency for BDI structure with small area, a four-transistor amplifier with a gain of 82dB is designed. The charge capacity of ROIC is also a key performance parameter when considering the noise and the large middle-wave and longwave photocurrent (up to 5nA and 100nA, respectively). A structure named double sharing capacitors (DSC) presented in this paper will be an effective solution to getting a large capacity in the limited 50 μm x 50 μm pitch area. DSC means that each integrating capacitor has two kinds of shares. One is between the integrating capacitor and another integrating capacitor which is in the adjacent pixel, and the other is between the integrating capacitor and the holding capacitor in the same pixel. By adopting the 0.35μm 2P4M mixed signal process, the DSC architecture can make the total effective charge capacity as high as 70Me- per pixel with 3V output range. According to the simulation results, this circuit works well under 5V power supply and achieves 2.5MHz data transmission rate, less than 0.1% nonlinearity. Its total power consumption is less than 110mW.
In our study, we designed a 512×512 readout integrated circuit (ROIC) for N-on-P short wave infrared
(SWIR) detectors, which has the ability to operate with two capacitors for different input current levels
from very low background applications to daytime high illumination conditions. A buffered direct
injection (BDI) readout cell as input circuit provides a low input resistance, high injection efficiency,
and precise biasing voltage to the photodiode at low input currents. In order to reduce the noise of the
BDI readout cell, a high-performance single stage amplifier is devised, the gain of which reaches as
high as 50dB. The input MOSFET of the amplifier operates at sub-threshold region to keep the
photodiode at precise reverse bias and steady injection efficiency. At the same time, with the input
MOSFET at sub-threshold region, the current is smaller than at saturation region, and the power
dissipation is reduced to a low level. A sample and hold circuit is also part of the input unit cell
architecture, which allows the infrared focal plane array (IRFPA) to be operated in full frame snapshot
mode and rolling mode. To prevent the excess of total current of the ROIC, the reset time of every row
has a lag of one period compared to the previous row. The simulation results confirm these advantages.
With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V, the well capacity
more than 1×10<sup>6</sup>e-, and the total power dissipation less than 120mW. The final chip is fabricated with
HHNEC 0.35um 1P4M process technology, and the pixel occupies a 30um×30um area. The Testing
results are coincide with the simulations of the circuit. With the detecting current varies from 30pA to
1nA, the linearity of BDI is 99%, and it can be operated at the temperatures below 77K.
In this paper, a new design of readout integrated circuit application in short wave infrared is introduced.
An amplifier of one transistor is employed in the CTIA to reduce the area of the unit cell. The output
unit cell achieved CDS (correlated double sampling) and SH (sample and hold) is designed for public
use of a whole line, and is outside the array. A new digital control structure of IRFPA ROIC is
presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than
regular lines, can be selected to readout. The structure of the circuitry and the operation principle are
analyzed, showing that the output dynamic range is over 2.5V, the cell capacity is more than 0.5Me<sup>-</sup> the
frame rate is 250Hz, and the linearity within working dynamic range is above 99.9 percent. This design
is going to be fabricated through Chartered 0.35um double-poly-four-metal (DPFM) process technique,
and the pixel occupies a 30um by 30um area.
With the development of the infrared focal plane detectors, the internal noises in the infrared focal
plane arrays (IRFPAs) CMOS readout integrated circuit gradually became an important factor of the
development of the IRFPAs. The internal noises in IRFPAs CMOS readout integrated circuit are
researched in this work. Part of the motivation for this work is to analyze the mechanism and influence
of the internal noises in readout integrated circuit. And according to the signal transporting process,
many kinds of internal noises are analyzed. According to the results of theory analysis, it is shown that
1/f noise, KTC noise and pulse switch noise have greater amplitude in frequency domain. These noises
have seriously affected the performance of output signal. Also this work has frequency test on the
signals of a readout integrated circuit chip which is using DI readout mode. After analyzing the
frequency test results, it is shown that 1/f noises and pulse switch noises are the main components of
the internal noises in IRFPAS CMOS readout integrated circuit and they are the noises which give a
major impact to the output signal. In accordance with the type of noise, some design methods for noise
suppression are put forward. And after the simulation of these methods with EDA software, the results
show that noises have been reduced. The results of this work gave the referenced gist for improving the
noise suppression design of IRFPAs CMOS readout integrated circuit.