In these days, the CMOS image sensors are commonly used in many low resolution applications because the CMOS
imaging system has several advantages against the conventional CCD imaging system. However, there are still several
problems for the realization of the single-chip CMOS imaging system. One main problem is the substrate coupling
noise, which is caused by the digital switching noise. Because the CMOS image sensors share the same substrate with
surrounding digital circuit, it is difficult for the CMOS image sensor to get a good performance. In order to investigate
the substrate coupling noise effect of the CMOS image sensor, the conventional CMOS logic, C-CBL
(Complementary-Current balanced logic) and proposed low switching noise logic are simulated and compared.
Consequently, the proposed logic compensates not only the large digital switching noise of conventional CMOS logic
,but also the huge power consumption of the C-CBL. Both the total instantaneous current behaviors on the power
supply and the peak-to-peak voltages of the substrate voltage variation (di/dt noise) are investigated. The simulation is
performed by AMI 0.5μm CMOS technology.