The tight overlay budgets required for 45nm and beyond makes overlay control a very important topic. High order
overlay control (HOC) is becoming an essential methodology to remove the immersion induced overlay signatures.
However, to implement the high order control into dynamic APC system requires FA infrastructure modification and a
stable mass production environment. How to achieve the overlay requirement before the APC-HOC system becomes
available is important for RD environment and for product early ramp up phase. In this paper authors would like to
demonstrate a field-by-field correction (FxFc) or correction per exposure (CPE) methodology to improve high order overlay signature without changing current APC-linear control system.
The minimum design rule of device patterns for LSI implant layers has been shrinking constantly according to the
industry requirements. Wavelength has been shortened and numerical aperture (NA) of the scanner has been enlarged to
catch up with the required shrinkage. Implant layers are unique because the resist is nearly always used without an
antireflective coating, and as a result, the resist is in direct contact with a multitude of substrate materials. In implant
applications, the wafer topography sacrifices some of the lithographic performance in order to obtain adequate features
on both top and bottom of the topography. KrF lithography has applied to most of the ion implant levels at today's
To solve the several issues in ion implant process, New KrF resist was designed specifically for the lithographic /
implantation process requirements.