Tight control of critical dimensions (CDs) of integrated circuit (IC) is required to achieve desired circuit performances, and getting more and more important as the IC CD shrinks. Phenomena and solutions of inter-field and intra-field CD errors have been widely studied for years. One of the well-known intra-field CD errors is so called the developer micro-loading effect due to the different pattern density loadings across the exposure field, in the other words, the more different the pattern density is, the more CD errors it would be expected. Some of the circuit layouts, e.g. thick gate oxide layers of dual gate oxide processes, and gate layers of embedded memory products, have this kind of across field pattern density concerns because of the different pattern density areas. Some researches showed that eliminating the by-products during the development process could reduce the developer micro-loading effect. With a multi-step development process (Puddle-Static Development-Dry-Puddle-Static Development-Rinse/Dry), the by-products can be removed and achieve a better CD uniformity. In this paper, optimization of the first puddle time in the multi-step development process is found to be the most critical to achieve uniform intra-field CDs. The purpose of the first puddle step is not only to remove the by-products but also to control the influence of the by-products to achieve uniform intra-field CDs. Once most of the by-products generated during the whole development process were carried away by the first puddle step, the optimum static Dev. time is needed to obtain the minimum intra-field CD difference. However, different photo-resists with different chemical formulations are expected to have identical optimum puddle time due to different chemical reactions of each by-product species, e.g. i-line PRs vs DUV PRs, or annealing type DUV PRs vs acetel type DUV PRs. These comparisons will be explained in details in this paper. Finally, the source of the by-products during the developer process was also identified to verify the validation of the multi-step developer process.
Optical resolution limit is one of the concerns for exposure tool selection. ArF lithography tools are the first choice for critical layers of 90 nm node with pitches narrower than 280 nm. However, high cost of ArF tools and photoresists make IC manufacturers try to seek for alternatives. Extension of KrF lithography has been widely discussed. For mass production of 130 nm node, KrF lithography has been pushed hard to achieve 160 nm contact holes with 320 nm pitch. In this paper, printing of via holes with the minimum pitch of 280 nm has been demonstrated with a special designed multi-pole aperture and high NA KrF lithography. With these illumination settings, reasonable process windows through all the pitches can be achieved for mass production of 90 nm node logic devices. Multi-pole illumination aperture settings are critical for balancing through-pitch process margins. Forbidden regions should not be found with optimum multi-pole illumination settings. In other words, the adequate combinations of multi-pole sizes and locations can minimize the forbidden proximity behavior and also keep the aerial imaging contrast balance through all the pitches. Mask bias is another factor to enlarge the common process windows. The process margin depth of focus (DOF) and mask enhanced error factor (MEEF) are investigated with various multi-pole settings and mask biases. Simulation works have been done for fine-tuning of the multi-pole aperture to reduce through pitch MEEF and optimize mask biases.