The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.
Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.
Directed self-assembly (DSA) with block-copolymers (BCP) is a promising lithography extension technique to scale below 30nm pitch with 193i lithography. Continued scaling toward 20nm pitch or below will require material system improvements from PS-b-PMMA. Pattern quality for DSA features, such as line edge roughness (LER), line width roughness (LWR), size uniformity, and placement, is key to DSA manufacturability. In this work, we demonstrate finFET devices fabricated with DSA-patterned fins and compare several BCP systems for continued pitch scaling. Organic-organic high chi BCPs at 24nm and 21nm pitches show improved low to mid-frequency LER/LWR after pattern transfer.
Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.
The printing of contact holes using positive tone development typically requires the interference of more than the 0th and 1st diffracted orders. In the 2d case and cQuad illumination in a positive tone process, if (0,0), (±1,0), and (0,±1) are exclusively present, the relevant contrast for imaging can in the best case not rise above 0.33, which is typically insufficient for a good process window. And this maximum value can only be achieved if the (0,0) and (±1,0) orders are matched to give a perfect sine wave of perfect contrast in y while the (0,0) and (0,±1) orders yield perfect contrast in x. In reality, the contrast is quite a bit lower. On the other hand, for negative tone development we are interested in the minima of the intensity–the dark locations in the image–and if we can manage to reduce the intensity in the minima we can achieve a high contrast image. Through a choice of RET and illumination, we manage to achieve a resolution for contact holes in 2d at k1 values that can otherwise be achieved only for 1d imaging.
Earlier work has been done on double exposures that exposed in the same resist a horizontal grating with x-dipoles and subsequently a vertical grating with y dipoles, without intermediate process steps. This yielded a high contrast image in resist at k1 <0.3.1 We show that an equivalent result can be achieved in a single exposure with a single mask, at admittedly high dose. We investigate the process parameters and the related mask tolerances, and find a non-intuitive result for the mask pattern that yields an optimized image at given mask specifications. Finally, we investigate the extension of this technique to EUV through simulations and experiments.
To extend scaling beyond poly(styrene-b-methyl methacrylate) (PS-b-PMMA) for directed self-assembly (DSA), high quality organic high-x block copolymers (HC series) were developed and applied to implementation of sub-10 nm L/S DSA. Lamellae-forming block copolymers (BCPs) of the HC series showed the ability to form vertically oriented polymer domains conveniently with the in-house PS-r-PMMA underlayers (AZEMBLY EXP NLD series) without the use of an additional topcoat. The orientation control was achieved with low bake temperatures (≤200 °C) and short bake times (≤5 min). Also, these process-friendly materials are compatible with existing 193i-based graphoepitaxy and chemoepitaxy DSA schemes. In addition, it is notable that 8.5 nm organic lamellae domains were amenable to pattern development by simple dry etch techniques. These successful demonstrations of high-x L/S DSA on 193i-defined guiding patterns and pattern development can offer a feasible route to access sub-10 nm node patterning technology.
A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.
Proc. SPIE. 9423, Alternative Lithographic Technologies VII
KEYWORDS: Electron beam lithography, Polymethylmethacrylate, Etching, Image segmentation, Composites, Scanning electron microscopy, Photomasks, Directed self assembly, Picosecond phenomena, System on a chip
Diminishing error tolerance renders the customization of patterns created through directed self-assembly (DSA) extremely challenging at tighter pitch. A self-aligned customization scheme can be achieved using a hybrid prepattern comprising both organic and inorganic regions that serves as a guiding prepattern to direct the self-assembly of the block copolymers as well as a cut mask pattern for the DSA arrays aligned to it. In this paper, chemoepitaxy-based self-aligned customization is demonstrated using two types of organic-inorganic prepatterns. CHEETAH prepattern for “CHemoepitaxy Etch Trim using a self-Aligned Hardmask” of preferential hydrogen silsesquioxane (HSQ, inorganic resist), non-preferential organic underlayer is fabricated using electron beam lithography. Customized trench or hole arrays can be achieved through co-transfer of DSA-formed arrays and CHEETAH prepattern. Herein, we also introduce a tone-reversed version called reverse-CHEETAH (or rCHEETAH) in which customized line segments can be achieved through co-transfer of DSA-formed arrays formed on a prepattern wherein the inorganic HSQ regions are nonpreferential and the organic regions are PMMA preferential. Examples of two-dimensional self-aligned customization including 25nm pitch fin structures and an 8-bar “IBM” illustrate the versatility of this customization scheme using rCHEETAH.
A viable pattern customization strategy is a critical to continue fin pitch scaling. Analysis shows that a self-aligned customization scheme will be required for fin pitch scaling beyond 20nm. In this paper, we explore scaling of the Tone-Inverted Grapho-Epitaxy technique with 24nm pitch PS-b-PMMA polymer to create groups of fins with self-aligned spaces in between. We discuss material selection, self-aligned customization, and etch processes to form 24-nm-pitch fins on silicon on insulator substrates. We demonstrate two-dimensional pattern customization at 24nm pitch, confirming scalability of this approach. FinFET device integration results at both 28 and 24 nm pitches shows a promising path for continued fin pitch scaling.
We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication . Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before , we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.
EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.
We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.
The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on
an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy
guiding pattern was created by the IBM Almaden approach using brush materials in
combination with an optional chemical slimming of the resist lines. Critical dimension (CD)
uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of
the DSA process were characterized. CD rectification and LWR reduction were observed. The
chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly
improving the DSA PW under over-dose conditions. However, the overall PW was found to be
smaller than without using the slimming, due to a new failure mode at under-dose region.
CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization
by various pre- and post-treatments has enabled robust pattern transfer down to 40nm
pitch. A systematic study of the parameters impacting this phenomenon will be shown.
Other challenges for patterning devices include profile control and material loss during
gate stack patterning and spacer formation. Lastly, initial patterning experiments at an
even more aggressive pitch show that the mechanical failure previously observed for
larger pitches once again becomes an increasingly important issue to consider.