Due to the semiconductor industry’s ever increasing need for finer resolution and improved critical dimension (CD) control, negative tone development (NTD) photoresists (resists) have been adopted for several advanced applications in lithographic patterning. NTD resists enable brightfield imaging by using an organic solvent developer to penetrate and remove the unexposed regions of the resist . For certain critical patterning layers, such as metal trenches and vias, NTD resists are able to provide better resist imaging quality compared to the previous positive tone development (PTD) resist process. However, there are several additional engineering difficulties which must be addressed for an NTD resist process. Specifically, NTD resists have low contrast organic solvent development and in an NTD process the material remaining on the wafer substrate is exposed resist which has been substantially transformed both chemically and mechanically. Therefore, the remaining exposed resist shows significantly more complex physical behavior than the remaining PTD resist and these behaviors require substantial improvement in an OPC (compact) model’s physical modeling accuracy in order to match wafer data and trends [2,3]. Additionally, these more complex resist behaviors place further requirements on the physical validation of OPC modeling inference. In this paper, we present results of our work to understand and improve the optimization and physical validation of physics-based NTD compact modeling flows by utilizing new methods for analysis and automation. We utilize a complete compact model flow containing physics-based resist model forms for chemically amplified resist (CAR) exposure, CAR reaction-diffusion, resist top-loss due to exposure combined with post-exposure bake (PEB), low contrast organic solvent development of resist, and mechanical deformation effects in multiple process steps. We present solid evidence that this physically-based flow has been validated for accuracy and predictability by comparing it to several experimental NTD datasets and to results of rigorous 3D lithography simulation models which were trained to fit other experimental NTD data. We additionally compared key physics-based model forms from the compact model to the more complex full time-based moving surface NTD models of the rigorous 3D simulation. We next analyzed the key physics-based compact model forms for sensitivity to input testpattern type, layout and mask dimension (e.g., linearity and MEEF), traditional dose-focus variations, as well as systematic and random noise in CD metrology. We present the results of this study and make recommendations for minimum testpattern and overall process space data to include in NTD compact model datasets. We also present flow benefits obtained from automating different validation tests including the usefulness of employing rigorous lithography simulation NTD results early in the compact modeling flow to improve overall model quality.  S-H. Lee, et all. Understanding dissolution behavior of 193-nm photoresists in organic solvent developers.
The model accuracy for Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) applications is a critical factor for patterning success in advanced technology nodes. One difficult challenge has been the accurate and fast simulation of Negative Tone Development (NTD) photoresist processes. It has been widely observed that CD measurements, top-down SEM contour images and X-section or AFM resist side wall profile measurements cannot be adequately predicted by conventional lithography process models, e.g., . Therefore, conventional OPC models were often unable to meet the demanding accuracy requirements of advanced logic or memory manufacturing. A key to achieving the demanding model accuracy requirements in NTD photoresist processes is to consider the photoresist shrinkage effects both in the Post-Exposure-Bake (PEB) step and photoresist development process step. Starting from continuum elastic mechanics, e.g., , we have developed a fast and accurate full 3D compact shrinkage model and validated its accuracy and usefulness vs. experimental results for several advanced processes and vs. rigorous simulation using a full physical lattice model. The compact model captures the significant photoresist shrinkage and deformation behaviors such as surface topography, resist sidewall angle (SWA) and layout pattern dependency , with much faster runtime capable of use in OPC and ILT mask data optimization. The speed and flexibility of the model are such that it can also be applied to help increase accuracy of simulation for some complex physical behaviors seen in other photoresist processes such as EUV and positive tone develop (PTD) photoresist.
The optical proximity correction (OPC) model and post-OPC verification that takes the developed photoresist (PR) 3D profile into account is needed in the advanced 2Xnm node. The etch process hotspots caused by poor resist profile may not be fully identified during the lithography inspection but will only be observed after the subsequent etch process. A complete mask correction that targets to final etch CD requires not only a lithography R3D profile model but also a etch process compact model. The drawback of existing etch model is to treat the etch CD bias as a function of visibility and pattern density which do not contain the information of resist profile. One important factor to affect the etch CD is the PR lateral erosion during the etch process due to non-vertical PR side wall angle (SWA) and anisotropy of etch plasma source. A simple example is in transferring patterns from PR layer to thin hard mask (HM) layer, which is frequently used in the double pattern (DPT) process. The PR lateral erosion contributes an extra HM etch CD bias which is deviated from PR CD defined by lithography process. This CD bias is found to have a nontrivial dependency on the PR profile and cannot be described by the pattern density or visibility. In this report, we study the etch CD variation to resist SWA under various etch conditions. Physical effects during etch process such as plasma ion reflection and source anisotropy, which modify the local etch rate, are taken into considerations in simulation. The virtual data are generated by Synopsys TCAD tool Sentaurus Topography 3D using Monte Carlo engine. A simple geometry compact model is applied first to explain the behavior of virtual data, however, it works to some extent but lacks accuracy when plasma ion reflection comes into play. A modified version is proposed, for the first time, by including the effects of plasma ion reflection and source anisotropy. The new compact model fits the nonlinear etch CD bias very well for a wide range of resist SWAs from 65 to 90 degrees, which covers the resist profile diversities in most real situations. This result offers a potential application for both resist profile aware and etch process aware mask correction model in the mask synthesis flow.
The Optical Proximity Correction (OPC) model, a key to process yield in the mask synthesis flow, is getting more and more complicated and challenging at advanced technology nodes (1X nm). To achieve accurate critical dimension (CD) prediction and model robustness on varied designed patterns, a rigorously tuned compact model (RTCM)  that takes the photoresist chemical effects into considerations is strongly desired. A lithography process consists of three main stages: Exposure, Post-Exposure Bake (PEB), and Photoresist Development. Each stage is characterized by its fundamental physics or chemistry that governs the process of illumination induced photo-acid generation, thermally activated chemical reaction-diffusion, and developer dependent photoresist dissolution, respectively. The final resist profile is determined by the process details of all these stages directly or indirectly. For an ideal resist that the development contrast approaches infinity, resist development is aptly represented by a threshold model applied to the PEB latent image (acid or inhibitor concentration). So the quality of OPC modeling is largely determined by the fidelity of PEB latent image [2,3]. However, for some types of resist and developer used in Negative Tone Development (NTD), the development contrast shows a long tail without a sharp transition. For such low-contrast resist, the developed resist profile is no longer described well by the equilevel surface of PEB latent image. Going beyond the threshold approximation, we start from the fundamental equations of resist development physics and analyze the time evolution of development front that determines the resist profile. In this paper, a new compact model is derived to catch the main physics in resist Development, which is also simple and computationally efficient to suit for OPC applications. Comparison with S-LITHO rigorous solutions and real-wafer experiments with 1D and 2D test patterns have showed that the new compact model, with fewer free parameters, provides better CD prediction than the existing empirical lumped parameter models for low-contrast resists. The new physical compact model offers a more accurate and extendable solution for OPC modeling at the 10nm node and onward.
3D Resist profile aware OPC has becoming increasingly important to address hot spots generated at etch processes
due to the mass occurrence of non-ideal resist profile in 28nm technology node and beyond. It is therefore critical to
build compact models capable of 3D simulation for OPC applications. A straightforward and simple approach is to
build individual 2D models at different image depths either based on actual wafer measurement data or virtual
simulation data from rigorous lithography simulators. Individual models at interested heights can be used by
downstream OPC/LRC tools to account for 3D resist profile effects. However, the relevant image depths need be
predetermined due to the discontinuous nature of the methodology itself. Furthermore, the physical commonality
among the individual 2D models may deviate from each other as well during the separate calibration processes. To
overcome the drawbacks, efforts are made in this paper to compute the whole bulk image using Hopkins equation in
one shot. The bulk image is then used to build 3D resist models. This approach also opens the feasibility of
including resist interface effects (for example, top or bottom out-diffusion), which are important to resist profile
formation, into a compact 3D resist model. The interface effects calculations are merged into the bulk image
Hopkins equation. Simulation experiments are conducted to demonstrate that resist profile heavily rely on interface
conditions. Our experimental results show that those interface effects can be accurately simulated with reference to
rigorous simulation results. In modeling reality, such a 3D resist model can be calibrated with data from discrete
image planes but can be used at arbitrary interpolated planes. One obvious advantage of this 3D resist model
approach is that the 3D model is more physically represented by a common set of resist parameters (in contrast to
the individual model approach) for 3D resist profile simulation. A full model calibration test is conducted on a
virtual lithography process. It is demonstrated that 3D resist profile of the process can be precisely captured by this
method. It is shown that the resist model can be carried to a different lithography process with same resist setup but
a different illumination source without model any accuracy degradation. In an additional test, the model is used to
demonstrate the capability of resist 3D profile correction by ILT.
With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.
A single compact resist model capable of predicting 3D resist profile is strongly demanded for the advanced technology
nodes to avoid the potential hotspots due to imperfect resist pattern shape and its lack of resistance in the subsequent
etch process. In this work, we propose a resist 3D (R3D) compact model that takes acidz-diffusion effect into account.
The chemical reaction between acid and base along z-direction is treated as second order effect that is absorbed into the
anisotropic diffusion length as a fitting parameter. Meanwhile, the resist model in the x-y wafer plane is still kept in
general by applying the compact solution of 2D reaction-diffusion equation. In order to have the 2D contour
predictability at arbitrary resist height, calibration from entire 3D data (CDs at several heights) areconducted
simultaneously witha single cost function so that the R3D compact model is described by a common set of resist free
parameters and threshold for all resist heights. With the low energy approximation, the acid z-diffusion effect is
equivalent to a z-diffused TCC that takes the form of linear combination of pure optical TCCs sampled at discrete
image-depth which can be pre-calculated. With this benefit, the R3D compact model offers a more physical approach but
adds no runtime concern on the OPC and verification applications. The predicted resist cross-section profiles from our
test patterns are compared those computed with rigorous lithography simulator SLITHO and show very good matching
results between them. The demonstration of the AF printability check from the predicted cross-section profile at AF
indicates the success of our R3D compact model.
Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.
Extreme ultraviolet (EUV) lithography is one of the leading technologies for 16nm and smaller node device patterning.
One patterning issue intrinsic to EUV lithography is the shadowing effect due to oblique illumination at the mask and
mask absorber thickness. This effect can cause CD errors up to a few nanometers, consequently needs to be accounted
for in OPC modeling and compensated accordingly in mask synthesis. Because of the dependence on the reticle field
coordinates, shadowing effect is very different from the traditional optical and resist effects. It poses challenges to
modeling, compensation, and verification that were not encountered in tradition optical lithography mask synthesis.
In this paper, we present a systematic approach for shadowing effect modeling and model-based shadowing
compensation. Edge based shadowing effect calculation with reticle and scan information is presented. Model calibration
and mask synthesis flows are described. Numerical experiments are performed to demonstrate the effectiveness of the
A technique traditionally used for optical proximity correction (OPC) is extended to include topography
proximity effects (TPE). Central to this is a thin-mask imaging model capable of addressing very large areas.
This compact model being compatible with traditional fast imaging models used in OPC can then be used in
standard correction approaches, compensating for both the optical proximity effects and wafer topography
proximity effects. Model origin and model form are considered along with calibration process. Capturing
ability and performance of the model are numerically evaluated on a number of test patterns. The performance
of the model is close to that of models used in the planar case.
EUV lithography is widely viewed as a main contending technology for 16nm node device patterning.
However, EUV has several complex patterning issues which will need accurate compensation in mask
synthesis development and production steps. The main issues are: high flare levels from optical element
roughness, long range flare scattering distances, large mask topography, non-centered illumination axis
leading to shadowing effects, new resist chemistries to model very accurately, and the need for full reticle
optical proximity correction (OPC). Compensation strategies for these effects must integrate together to
create final user flows which are easy to build and deploy with reasonable time and cost. Therefore,
accuracy, usability, speed and cost are important with methods that have considerably more complexity
than current optical lithography mask synthesis flows.
In this paper we analyze the state of the art in accurate prediction and compensation of several of these
complex EUV patterning issues, and compare that to 16nm node expected production needs. Next we
provide a description of integration issues and solutions which are being implemented for 16nm EUV
process development. This includes descriptions of OPC model calibration with flare, shadowing, and
topography effects. We also propose a realistic (in terms of accuracy and mask area) flare parameter calibration flow to improve short and longer range flare correction accuracy above what can be achieved with only a measured EUV flare PSF.
Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm
lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of
optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of
wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer
topography (proximity) effects induced by different optical properties of the patterned materials start playing
a significant role, and correction techniques need to be applied in order to minimize the impact.
In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC
procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through
the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask
A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using
extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer
A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as
well as wafer topography is used to generate virtual measurement data, which are used for model calibration
as well as for model validation.
For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a
planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test
patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental
data, including hybrid approaches where only experimental data from planar substrates is available and a
corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer
We analyze the relevant effects and requirements for model building and validation as well as the
performance of fast WTPC models.
Photolithography on reflective surfaces with topography can cause overexposure in some areas in the photoresist,
resulting in undesired critical dimension (CD) variations in the printed patterns. Using bottom anti-reflective coatings
(BARCs) will reduce the severity of the problem. However it is not a preferred solution in some situations due to added
process complexity, such as the case of implant blocking layer patterning. This topography proximity effect (TPE) has
been ignored in the mask synthesis flow for the 45nm and larger nodes due to its relatively small impact to the CDs.
When the device critical length reaches 32nm and lower, the variations on the implant layer caused by underlying
topography becomes more and more an issue and need to be addressed properly. In order to do that, simulation with nonplanar
stack is required. The available tools for photolithography simulation with wafer topography, such as Synopsys'
Sentaurus Lithography (S-Litho), usually adopt a rigorous approach based on the solution of the Maxwell equations and
unsuitable for full chip optical proximity correction (OPC) due to their prohibitively long runtimes. A fast method for
TPE modeling is needed to make full chip TPE correction feasible.
In this paper, we propose a computationally fast approximate method that captures TPE well. It enables fast model
calibration and full chip implant layer mask correction, and fits in the current OPC flows easily. We validate the
method's effectiveness by comparing its simulation results with those produced by Sentaurus Lithography. We also
show how it helps implant layer mask synthesis that takes TPE from previous layers into consideration.
The concept of focus blur encompasses the effect of laser bandwidth longitudinal chromatic
aberration and scanner stage vertical vibration. The finite bandwidth of excimer laser source
causes a corresponding finite distribution of focal planes in a range of 100nm or larger for the
optical lithography system. Similarly, scanner vertical stage vibration puts the wafer in a finite
distribution of focal planes. Both chromatic aberration and vertical stage vibration could
introduce significant CD errors, hence can no longer be ignored in current lithography processes
development and OPC development that require CD control within a few nanometers. We
developed several methodologies to model the laser chromatic aberration and vertical stage
vibration in OPC (Optical Proximity Correction) modeling tool. Extensive simulations were done
to calculate chromatic aberration and vertical stage vibration focus blur's impact on lithography
patterning for a variety of test structures. Chromatic aberration and vertical stage vibration focus
blur effect was further included as an regression term in experimental OPC model calibration to
capture its impact on litho patterning, and significant benefit to OPC model calibration was
A thin membrane called a pellicle is commonly used to protect the mask from contamination. The thickness of the
pellicle material is usually optimized at normal incident angle to minimize the thin film optics interference effect by
cancellation of the reflected light from the top ambient/pellicle interface with the reflected light from the bottom
pellicle/ambient interface. In previous lithography generations the maximum angle collected by the projection lens (NA)
was low, hence the normal incidence approach was valid, and the transmission loss for the non-normal incident angles
was minor and ignored. With modern hyper-NA imaging for 45nm and smaller nodes, this transmission attenuation
becomes larger. The more stringent CD error budget of these technology nodes demands that this effect should not be
In this paper, we present a modeling framework that takes into consideration the high angle pellicle effects. Taking the
pellicle's polarization state dependent transmission data, which can be measured or computed with a rigorous simulator,
we first present the pellicle transmission property as Jones matrices on the pupil plane, and then incorporate pellicle
modeling into the existing vector model for lithography imaging computation. Existing modeling software for modelbased
OPC/RET tools is easily enhanced to include pellicle modeling. Using Synopsys' OPC/RET modeling software
ProGen, we investigate the necessity of pellicle effect modeling for mask synthesis for 45 nm and smaller nodes.
Numerical experiments are performed to study the impact of illumination polarization on the accuracy of lithography
simulation and the quality of OPC results.
High NA and Ultra-High NA (NA>1.0) applications for low k<sub>1</sub> imaging strongly demand the adoption of polarized
illumination as a resolution enhancement technology since proper illumination polarization configuration can greatly
improve the image contrast hence pattern printing fidelity and the effectiveness of optical proximity correction (OPC).
However, current OPC/RET modeling software can only model the light source polarization of simple types, such as TE,
TM, X, Y, or sector polarization with relatively simple configuration. Realistic polarized light used in scanners is more
complex than the aforementioned simple ones. As a result, simulation accuracy and quality of the OPC result will be
compromised by the simplification of the light source polarization modeling in the traditional approach. With ever
shrinking CD error budget in the manufacturing of IC's at advanced technology nodes, more accurate and
comprehensive illumination source modeling for lithography simulations and OPC/RET is needed. On the other hand,
for polarized illumination to be fully effective, ideally all the components in the optical lithography system should not
alter the polarization state of light during its propagation from illuminator to wafer surface. In current OPC modeling
tools, it is typically assumed that the amplitude and polarization state of the light do not change as it passes through the
projection lens pupil, i.e. the polarization aberration of projection lens pupil is ignored. However, in reality, the
projection lens pupil of the scanner does change the amplitude and the polarization state to some extent, and ignorance
of projection pupil induced polarization state and amplitude changes will cause CD errors un-tolerable at the 45nm
device generation and beyond.
We developed an OPC-deployable modeling approach to model arbitrarily polarized light source and arbitrarily
polarized projection lens pupil. Based on polarization state vector descriptions of a general illumination source, this
modeling approach unifies optical simulations of unpolarized, partially polarized, and completely polarized
illuminations. The polarization aberration imposed by the projection lens pupil is modeled via Jones matrix format, and
it is applicable to arbitrary polarization aberrations imposed by any components in the lithography system that can be
characterized in Jones matrix format. Numerical experiments were performed to study CD impact from illumination
polarization and projection lens pupil polarization aberrations, and up to several nanometers impact on optical proximity
effect (OPE) was observed, which is not negligible given the extremely stringent CD error budget at 45nm node and
beyond. Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better
approximation to the physical scanner projection pupil, we propose a more physics-centric methodology to evaluate the
optical model accuracy of OPC simulator.
Production optical proximity correction (OPC) tools employ compact optical models in order to accurately
predict complicated optical lithography systems with good theoretical accuracy. Theoretical accuracy is
not the same as usable prediction accuracy in a real lithographic imaging system. Real lithographic
systems have deviations from ideal behavior in the process, illumination, projection and mechanical
systems as well as in metrology. The deviations from the ideal are small but non-negligible. For this study
we use realistic process variations and scanner values to perform a detailed study of useful OPC model
accuracy vs. the variation from ideal behavior and vs. theoretical OPC accuracy. The study is performed
for different 32nm lithographic processes. The results clearly show that incorporating realistic process,
metrology and imaging tool signatures is significantly more important to predictive accuracy than small
improvements in theoretical accuracy.
The concept of focus blur encompasses the effect of laser bandwidth longitudinal
chromatic aberration and scanner stage vertical vibration. The finite bandwidth of
excimer laser source causes a corresponding finite distribution of focal planes in a range
of 100nm or larger for the optical lithography system. Similarly, scanner vertical stage
vibration puts the wafer in a finite distribution of focal planes. Both chromatic aberration
and vertical stage vibration could introduce significant CD errors, hence can no longer be
ignored in current lithography processes development and OPC development that require
CD control within a few nanometers. We developed several methodologies to model the
laser chromatic aberration and vertical stage vibration in OPC (Optical Proximity
Correction) modeling tool. Extensive simulations were done to calculate chromatic
aberration and vertical stage vibration focus blur's impact on lithography patterning for a
variety of test structures. Chromatic aberration and vertical stage vibration focus blur
effect was further included as an regression term in experimental OPC model calibration
to capture its impact on litho patterning, and significant benefit to OPC model calibration
The increasingly stringent demand for shrinkage of IC device dimensions has been pushing the development of new
resolution enhancement technologies in micro-lithography. High NA and Ultra-High NA (NA>1.0) applications for low
k<sub>1</sub> imaging strongly demand the adoption of polarized illumination as a resolution enhancement technology since
proper illumination polarization configuration can greatly improve the image contrast hence pattern printing fidelity.
For polarized illumination to be fully effective, ideally all the components in the optical system should not alter the
polarization state during propagation from illuminator to wafer surface. In current OPC modeling tools, it is typically
assumed that the amplitude and polarization state of the electric field do not change as it passes through the projection
lens pupil. However, in reality, the projection lens pupil of the scanner does change the amplitude and the polarization
state to some extent, and ignorance of projection pupil induced polarization state and amplitude changes may cause CD
errors which are un-tolerable at the 45nm device generation and beyond.
We developed an OPC-deployable modeling approach to model polarization aberration imposed by the projection lens
pupil via Jones matrix format. This polarization aberration modeling capability has been integrated into the Synopsys
OPC modeling tool, ProGen, and its accuracy and efficiency have been validated by comparing with an industry
standard lithography simulator SolidE. Our OPC simulations show that the impact of projection lens pupil polarization
aberrations on optical proximity effect (OPE) could be as large as several nanometers, which is not negligible given the
extremely stringent CD error budget at 45nm node and beyond. This modeling approach is applicable to arbitrary
polarization aberrations imposed by any components in the lithography system that can be characterized in Jones matrix
Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better approximation to
the physical scanner pupil, we propose a more physics-centric methodology to evaluate the optical model accuracy of
Recent research has shown that properly polarized light source enhances image contrast in photolithography for
manufacturing integrated circuit (IC) devices, thus improves the effectiveness of optical proximity correction (OPC) and
other resolution enhancement techniques (RET). However, current OPC/RET modeling software can only model the
light source polarization of simple types, such as TE, TM, X, Y, or sector polarization with relatively simple
configuration. Realistic polarized light used in scanners is more complex than the aforementioned simple ones. As a
result, simulation accuracy and quality of the OPC result will be compromised by the simplification of the light source
polarization modeling in the traditional approach. With ever shrinking CD error budget in the manufacturing of IC's at
advanced technology nodes, more accurate and comprehensive light source modeling for lithography simulations and
OPC/RET is needed.
In this paper, we present a modeling framework that takes arbitrarily polarized light source. Based on polarization state
vector descriptions of the light source, it unifies optical simulations of unpolarized, partially polarized, and completely
polarized illuminations. We built this framework into Synopsys' OPC modeling tool ProGen. Combined with ProGen's
existing capability to handle vectorial aberration by the projection lens, large angle effects due to high NA, and thin film
effects, this framework represents a general vectorial model for optical imaging with the state-of-the-art scanners.
Numerical experiments were performed to study CD impact of various illumination polarization modeling schemes in
the context of OPC/RET.