As lithographic technology goes beyond the 45nm node, depth of focus (DOF) and
line width roughness (LWR) for poly gates have become critical parameters. There is a
growing interest in applying surface conditioner solutions during the post-develop
process to increase DOF and reduce LWR. Surface conditioners interact with resist
sidewall selectively, causing surface plasticization effect and smoothing the sidewall
profile. As a result, the LWR can be reduced and the poor pattern profile located in the
focus marginal area due to poor image contrast will be improved so that the depth of
focus (DOF) can be increased significantly. In this paper, the features of lines/spaces
patterned for the 45nm node by immersion lithography were used to evaluate surface
conditioner performance with regards to DOF increase and LWR reduction. The results
demonstrate there is about 1.5 nm LWR reduction, as well as a significant improvement
on the process window for DOF, for which there is 37.5% increase for ISO poly gates
and 36% increase for DENSE poly gates. No negative impact on the effect of optical
proximity correction (OPC) and resist profile were observed with the new process.
In addition, etch testing was conducted to determine how much post-develop LER
reduction has been retained through etch by comparing post-etch and post-develop LER
for both baseline and surface conditioner processes.
In this paper, we will demonstrate a novel approach to improve process window prediction capability. The new method, Lithography Manufacturability Check (LMC), will be shown to be capable of predicting wafer level CDs across an entire chip and the lithography process window with a CD accuracy of better than 10nm. The impact of reticle CD error on the weak points also will be discussed. The advantages of LMC for full chip process window analysis as well as the MEEF check to catch process weak points will be shown and the application to real designs will be demonstrated in this paper. LMC and MEEF checks are based on a new lithography model referred to as the Focus Exposure Matrix Model (FEM Model). Using this approach, a single model capable of simulating a complete range of focus and exposure conditions can be generated with minimal effort. Such models will be shown to achieve a predictive accuracy of less than 5nm for device patterns at nominal conditions and less than 10nm across the entire range of process conditions which define the nominal process window. Based on the inspection results of the full chip LMC check, we identify process weak points (with limited process window or excessive sensitivity to mask error) and provide feedback to the front end design stage for pattern correction to maximize the overall process window and increase production manufacturability. The performance and full function of LMC will also be described in this paper.
The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations.
Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.