By 2015 EUV pellicle development has made significant progress such that it is mature enough for production testing. To support the implementation of the pellicle, the current EUV Inner Pod (EIP) design is modified to accommodate the addition of a pellicle to the reticle, which primarily involves adding a pellicle pocket to the baseplate of the EIP. Working closely with an EUV lithography customer, Entegris has developed a pellicle-compatible EUV inner pod that has passed this customer’s testing. This paper presents the key design features of the Entegris pellicle-compatible EUV pod and the testing results. The non-pellicle EIP baseplate is a flat plate and is designed to maintain a very small distance from the underside (also pattern side) of the reticle. In the pellicle-compatible version a pocket is added to the baseplate to accommodate the pellicle and its frame. For compatibility purpose, the weight of the pellicle-compatible baseplate is kept about the same as the non-pellicle baseplates. In addition, considering that both non-pellicle and pellicalized reticles are going to be used by end users, a feature on the backside of the baseplate that’s different between the two versions is going to be used by a sensor in the lithography tool to tell whether it is a pellicle or non-pellicle pod. Test results from several critical defectivity tests are highlighted in this paper including: full system cycle test, reticle handling tests, venting tests, EIP outgassing tests, along with pod shipping test.
Electrostatic discharge (ESD) problem resulting from charges on wafers is a serious
concern in IC manufacturing processes. Even though micro-environments, such as a
FOUP or a SMIF pod, provide path to ground to conduct away charges on wafers,
this method cannot remove charges on the insulative features on a work-in-process
wafer. In this study, we integrated an ionization module to a FOUP purge system to
neutralize charges on wafers. With a full load of wafers, ionized nitrogen entered the
FOUP and effectively reduced the wafer charge level from 1,000 v/cm to 100 v/cm
within 5 minutes. The effectiveness of neutralizing charges and ease of integrating
with currently available purge facility enable this method a promising way to help
reduce wafer charges, thus reduce the possibility of ESD damages to ICs on wafer.
The same idea can be applied to reduce charges on reticles in a recticle pod.