As we move to more advanced nodes, the number of Chemical Mechanical Polishing (CMP) steps in semiconductor processing is increasing rapidly. CMP is known to suffer from pattern dependent variation such as dishing, erosion, recess, etc., all of which can cause performance and yield issues. One such yield issue seen in back end of line (BEOL) Cu interconnect CMP processes is pooling. Pooling exists when there is uncleared bulk Cu and/or barrier residue remaining after final CMP step, leading to shorts between neighboring interconnect lines. To detect potential pooling locations on a given design, for a given CMP process, predictive CMP models are needed. Such models can also aid in CMP process and chip design optimizations. In this paper we discuss how a pattern dependent CMP effect that we call the “local neighborhood effect” causes large recesses that can lead to pooling in Cu interconnect CMP processes. We also discuss modeling this effect as part of an advanced predictive CMP modeling system and show how the resulting modeling system accurately predicts Cu pooling on several 14 nm designs.
Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation.
PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.
Beyond 40 nm technology node, the pattern weak points and hotspot types increase dramatically. The typical patterns for
lithography verification suffers huge turn-around-time (TAT) to handle the design complexity. Therefore, in order to
speed up process development and increase pattern variety, accurate design guideline and realistic design combinations
are required. This paper presented a flow for creating a cell-based layout, a lite realistic design, to early identify
problematic patterns which will negatively affect the yield.
A new random layout generating method, Design Technology Co-Optimization Pattern Generator (DTCO-PG), is
reported in this paper to create cell-based design. DTCO-PG also includes how to characterize the randomness and
fuzziness, so that it is able to build up the machine learning scheme which model could be trained by previous results,
and then it generates patterns never seen in a lite design. This methodology not only increases pattern diversity but also
finds out potential hotspot preliminarily.
This paper also demonstrates an integrated flow from DTCO pattern generation to layout modification. Optical
Proximity Correction, OPC and lithographic simulation is then applied to DTCO-PG design database to detect hotspots
and then hotspots or weak points can be automatically fixed through the procedure or handled manually. This flow
benefits the process evolution to have a faster development cycle time, more complexity pattern design, higher
probability to find out potential hotspots in early stage, and a more holistic yield ramping operation.