In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant
progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the
development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution
limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for
developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as
complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization)
process have also applied as design rule is decreased, the improvement of process overlay control is very important.
In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual
experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with
comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the
process effects such as hard mask material, thermal process and CMP process that affect to overlay control.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size.
In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.
Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations.
In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.
Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at
k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process
window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT
(Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional
OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which
maximizes the process window subject to mask manufacturing constraints.
We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions
corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with
other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm
metal and contact layers and discuss the possibilities and the limitations of this new technology.
New concepts about transistor structure are being introduced for sub-50nm memory products. As the memory cell
design is shrinking down, conventional transistor of planar structure can not guarantee safe transistor operation.
Newly introduced transistor has to ensure robust transistor operation characteristics and process stability
simultaneously. One of the candidates which are being developed recently is vertical transistor. The basic layout to
integrate vertical transistor include very dense 2-dimensional features. The new memory cell based on dense structure
can also contribute to reduction of cell area compared to conventional memory cell such as 8F2 planar cell. While new
memory structure enables the reduction of chip size, its 2-dimensional structure limits resolving performance of optical
lithography inevitably. It is very challenging to build 4F2 dense features of sub-50nm node by single exposure
technology using hyper NA ArF lithography before the EUV era. In this paper, the feasibility of 2-dimensional dense
structure at 50nm node is presented and various techniques are introduced to realize new memory scheme as next
generation memory cell structure.