As integrated circuit technology advances and features shrink, the scale of critical dimension (CD) variations induced by
lithography effects become comparable with the critical dimension of the design itself. At the same time, each
technology node requires tighter margins for errors introduced in the lithography process. Optical and process models --
the black boxes that simulate the pattern transfer onto silicon -- are becoming more and more concerned with those
different process errors. As a consequence, an optical proximity correction (OPC) model consists mainly of two parts; a
physical part dealing with the physics of light and its behavior through the lithographical patterning process, and an
empirical part to account for any process errors that might be introduced between writing the mask and sampling
measurements of patterns on wafer. Understanding how such errors can affect a model's stability and predictability, and
taking such errors into consideration while building a model, could actually help convergence, stability, and
predictability of the model when it comes to design patterns other than those used during model calibration and
verification. This paper explores one method to quickly enhance model accuracy and stability.
It has been widely accepted that to ensure good yield in IC wafer manufacturing, early adaptation of DFM (Design for
Manufacturability) guidelines in design phase is required and it is particularly true in Foundry business. Integrated
foundry approaches for DFM guideline development were presented in this paper. With emphasis of process variations
and process sensitivity impact on design patterns, we describe the procedure of the combination of rule-based and
simulation-based lithographical hotspot pattern characterizations. An evaluation of process sensitivity metrics for
analyzing potential pattern hotspots is then described. In addition, based on hotspot pattern severity, repeated patterns
from different designs are saved into a pattern library as knowledge deposition tool and those patterns can be easily
identified later in new designs through pattern search, which is much faster than simulation based hotspot detections.
With this approach, a set of DFM compliance rules is derived to designs in the design implementation stage for both
110nm and 90nm technology nodes, striving to gain more yield, device performance, and improve time-to-volume
Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in
different designs within the same technology node and across different technology nodes, which eluded design rule
check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on
whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its
We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post
OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early
OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot
patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within
pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is
developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect
pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a
pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity,
but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either
exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each
other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs.
In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application
in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to
selected hot spot patterns will be shown.
In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the
candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole
patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process,
regarding porcess cost redcution and easy access to RETs.
In low-k1 imaging lithography process it is difficult to make the accurate OPC model not only because of factors caused
by unstable process such as large CD (Critical Dimension) variation, large MEEF (Mask Error Enhancement Factor) and very poor process window but also because of potential error factors induced during OPC model fitting. In order to minimize those issues it is important to reduce the errors during OPC modeling. In this study, we have investigated the most influencing error factors in OPC modeling. At first, through comparing influence of optical parameters and illumination systems on OPC runtime and model accuracy, we observe main error factor. Secondly, in the case of resist modeling, OPC runtime and model accuracy were also analyzed by various model forms.