The ability to transfer designs with high fidelity onto photomasks and then to silicon is an increasingly complex task for advanced technology nodes. For example, the majority of the critical layers for even the 130nm node are patterned by sub-wavelength photolithography; therefore, the numerical aperture, illumination condition, and the resist process must be optimized to achieve the necessary resolution. The reticle, as a bridge between design and process, has become very complex due to the extensive application of resolution enhancement technologies (RETs). As the complexity of RETs increases, the final mask data can be vastly different from the original design due to a series of data manipulations. Optimizing the reticle layout plays the pivotal role in design-for-manufacturability (DFM) considerations.
In this paper, we will discuss how design rules must accommodate the needs of Optical Proximity Correction (OPC) and Phase-shifting Masks (PSM). The final layout on a mask after extensive polygon manipulation must also meet the capability and manufacturability of mask writing, mask inspection, and silicon processing. We will also discuss how the wafer fab's perspective can affect the mask shop. Throughout the discussion, we will demonstrate that the integration at mask level and the collaboration of design, RET, mask shop, and wafer fab are key to DFM success.
Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.
Printing small geometries using wavelength of 248 nm on low- k materials is not a plug-in photolithography process from one technology to other technology node. In this paper, a method of film characterization of low-k dielectric materials will be discussed. For a characterization of chemical vapor deposited low-k dielectric materials, a positive tone deep UV (DUV) chemically amplified photoresist (CAR) was used as a poisoning gauge. In early development state of low-k dielectrics and copper dual damascene interconnects in back-end-of-line processes, unstable patterning behaviors were observed in spite of using an organic bottom antireflective coating layers on low-k substrates. The initial work was focused on finding the source of lot-to-lot critical dimension (CD) variations and understanding what causes this problem as well. Study indicated a strong correlation that photo CD depended on time interval between photolithography process and previous process step. Significant photo CD shift was introduced by short cycle time from thin film deposition to photolithography process and post via etch clean process to trench photolithography process. To minimize photo CD variations, the process optimizations were necessary in low- k dielectric film deposition, rework, via etch process, and post via etch clean process. As parallel efforts to improve lot-to-lot CD control, various photoresist system, different ambient annealing conditions, various surface organic and inorganic capping techniques were tested. In this experiments, time interval between processes was tightly controlled and maximized the worst case of scenario. Fresh and aged low-k dielectric films were analyzed using time-of- flight secondary ion mass spectrometry and x-ray photoelectron spectroscopy techniques. This work suggested that N2 containing in the film or introducing N2 into low-k dielectric film caused lot-ot-lot photo CD variations.