In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.
Small contact holes are the most difficult structures for microlithography to print because it is sensitively affected by the process condition, pattern density and environment as well. Moreover, the patterning of very small contact hole features for the 60nm node DRAM device generation will be a difficult challenge for 248nm lithography. However, we have already demonstrated the applicability of thermal flow resist to print 80nm contact holes for DRAM device using 248nm lithography in previous studies. In this work, we study the potential for contact photoresist reflow to be used with 248nm photoresist to increase process windows of small contact dimensions at the 60nm node DRAM device generation (0.21 k1). With KrF 0.80NA scanner, resist flow process and layout optimization were carried out to achieve the contact hole patterning. And also the exposure condition was optimized. For a contact hole with CDs of 69nm +/- 10%, Focus-Exposure windows over the wafer are 0.25μm and 8%, respectively. In conclusion, we have successfully achieved the contact hole patterning with KrF resist flow process for the 60nm node DRAM device.
One of the crucial tasks of semiconductor process is reduction of manufacturing cost by shrinking the design rule with the help of fine patterning technologies. For high density DRAM application, we explored 0.29 k1 lithography with KrF 0.80NA scanner. Well-known lithography technologies such as asymmetric crosspole, dipole illumination and 6% attenuated PSMs were used for this experiment. Illumination source and mask layout optimization were carried out iteratively to meet CD target, and high contrast thin resist was applied to improve pattern fidelity. Some of the biggest challenges were coping with large MEEF and reducing simulation error. Abnormal non-open fail, probably due to large MEEF, was observed at a dense contact hole pattern. To cope with non-open fail, we tested multi-PSM which composed of alternating PSM along the x-axis direction and 6% attenuated PSM along the y-axis direction. Also we pushed sigma offset of illumination pupil more strongly than exposure tool's specification and there was no serious drawbacks of partial coherency extension. Accurate partial coherence measurement was important for obtaining target CDs and reducing OPC error. For some layers, unexpected simulation error was occurred especially at the patterns of peripheral circuit, therefore we had to calibrate simulation parameters of in-house tool and commercial tool (Solid-C) for OPC simulation. Finally we successfully demonstrated 0.29k1 KrF lithography by showing process yield over 58% in 512Mb DRAM having design rule of 90nm. Based on the results we obtained, we can conclude that 0.29k1 lithography is quite feasible for mass production and 60nm design rule DRAM devices can be manufactured with ArF dry 0.93NA. Since dry 0.93NA corresponds to 1.33NA in ArF water immersion with respect to k1, we can expect that it is possible to fabricate 42nm DRAM devices with ArF immersion lithography.
Currently, 193nm lithography including contact hole patterning is being integrated into manufacturable process at 80nm technology nodes. However, for 193nm contact hole patterning, many researchers have reported various troubles such as poor profiles, low exposure dose, and pattern edge roughness due to inherent flaws of ArF resist materials. Also, it is desirable to be extended the KrF lithography at a cost. Of course, the patterning of very small contact hole features for the 80nm DRAM device generation will be a difficult challenge for 248nm lithography. In this work, we study the potential for contact photoresist reflow to be used with 248nm photoresist to increase process windows of small contact dimensions at the 80nm DRAM device generation. In KrF 0.80NA scanner, resist flow process and layout optimization was carried out to achieve the contact hole patterning. The contact CD at best focus is 140nm and the amount of photoresist flow is approximately 52nm. For a contact hole with CDs of 88nm +/- 10%, Focus-Exposure windows over the wafer are 0.3um and 10%, respectively. In conclusion, we have successfully achieved the contact hole patterning with KrF resist flow process for 80nm DRAM device.
95nm KrF lithography has been developed for 512 Mb DRAM. KrF 0.80NA scanner was used to print 190nm pitch patterns and this means the process factor k1 is 0.306. Crosspole illumination was used to print critical layers, which has four poles on x and y-axis. To improve CD uniformity of critical layers we also used fogging effect corrected (FEC) reticles and thin photo resist process, which needs the hard mask etching process to overcome poor dry etch resistance. For 95nm DRAM cell patterns, we could get more than 8% exposure latitude (EL) and 0.3 μm depth of focus (DOF). With FEC masks and optimized resist process, CD uniformity of word line layer printed on wafer was less than 10nm. Overlay accuracy of critical layers is mostly less than 25nm. However at core and periphery area of DRAM the extreme off-axis illumination like crosspole brought poor process latitude in weak zone duties and therefore the hard optical proximity correction (OPC) work was required. In a real integration other novel technologies are used such as gap-filling for STI and ILD processes, Wsi gate, W bit line and SAC processes. This paper reported only lithographic performance for printing 95nm DRAM patterns. Consequently KrF lithography is still promising technology to print sub 100nm node DRAM.
In ArF (193nm) lithography, severely sloped pattern profiles have been observed particularly in COMA type resists. In using COMA resists that are relatively absorbent, such crude profiles result in obstacles to litho-process reliability and stability. To improve weak profiles, the effects of Alkali Treatment (AT) on the surface of coated ArF resist film are explored because it is expected that Alkali Treatment works as additive quenchers in top area of resist film, and then latent image contrast can be improved consequently. For this experiment, TMAH (2.38wt%) developer was used as alkali solution and two kinds of ArF resist were used with in-house ArF resist (COMA type) and the commercial resist (Acrylate type). An appropriate Alkali Treatment was found to be effective for good profiles without thickness loss in COMA type but not for the Acrylate resist. In this paper, Alkali Treatment effects and process conditions suitable to obtain good patterns as well as considerable process margin (EL, DOF) will be discussed.