As VLSI products are being developed rapidly, design rules of semiconductor devices are correspondingly shrinking. Therefore, the electric couplings between adjacent lines are increasing and this phenomenon requires control of critical dimension uniformity (CDU) more tightly. In addition to that, the development of lithography tool for sub- 40nm design rule (D/R) is being delayed, which makes most IC manufacturer drive double patterning technology (DPT) as next generation lithography (NGL) solution. CD control is one of critical issues to implement DPT for mass production, because CD of 1st pattern affects the formation of 2nd pattern seriously so that the uniformity of 1st pattern is more important.
In this paper, the improvement of CD uniformity is investigated, especially for 3Xnm flash device for where double patterning technique is applied. Several methods have been considered or evaluated to improve CD uniformity. Among them, DoseMapperTM of ASML shows promising results. Using this system, in field uniformity (IFU) & in wafer uniformity (IWU) are improved 14% in 3&sgr;. To be implemented as a technology for mass production and to maintain the best performance, several efforts in terms of metrology and process will be further discussed in this paper.
In optical lithography, small space patterning is the most difficult task. The direct small-space patterning is not good enough with resolution enhancement technique (RET) in sub-80 nm level. Two sequential processes normally achieve the small space. Once the pattern is forming a larger pattern normally, and then makes them shrink to fit to the designed size by additional process. Usually resist thermal flow process has been used to obtain small space as additional process, which has several process issues such as flow amount control of isolated and dense small contacts, uniformity degradation and bowing profile. In order to solve these issues, we introduced the resolution enhancement lithography assisted by chemical shrink (RELACS) and shrink assist film for enhancement resolution (SAFIER) process in ArF lithography. In this paper, the RELACS and SAFIER process are compared with the resist thermal flow process for sub-80 nm space using ArF exposure tool. With the application of this process, we confirmed the improvement of in-wafer uniformity and the successful implementation of sub-80nm small space patterning regardless of pitch size and pattern arrangement.
Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell and logic patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 90 nm node DRAM and logic layers concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. We also introduced concept of checkerboard CLM to apply zigzag L/S and semi dense contact in the logic layer. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by 10~15% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 90 nm node DRAM satisfied 8% of EL (Exposure Latitude) and 0.3 μm of DoF (Depth of Focus) margin. Also 3D mask topographic effect of CLM in the specific contact layer was discussed.
ArF resist systems have some serious stumbling block related to etch selectivity, pattern collapse, and pattern slimming during CD-SEM measurement. Among these problems, when exposed to electron beam, the linewidth reduction of resist features is the main topic in our study. Since the pattern slimming may result in accuracy error of measurement and potential device reliability issues due to permanent deformation, any method to improve this undesired phenomenon should be found. In this paper, the anti-shrinkage coating approach as a method to improve pattern slimming during SEM measurement will be described. The Anti-Shrinkage Coating (ASC) material consists of anti-shrinking water-soluble polymers and other additives (e.g. cross-linker). The ASC method is a chemical attaching process that includes simple coating, mixing, baking, and rinse steps with DI water, applied after conventional photolithography. The ASC method results that the pattern shrinkage during SEM measurement is reduced less than a half of the resist alone. Additionally, the employment of the ASC method gives rise to improve pattern fidelity and LER, which are serious problems in ArF lithography. Finally, we expect that the ASC method can contribute to form the critical small space patterns.
KrF lithography around 0.3k1 was studied using high transmittance attenuated phase shifting mask(att.PSM). Although gradual transition to the more high NA KrF scanner or ArF scanner takes place, the strong requests for the timely process development to keep up with the rapid shrinkage of device drive the extension of lithography technology to the lower k1; 0.3 or even below.
Under the given illumination condition, aerial image contrasts for varying design rules(D/R) can be related to the transmittance of att.PSM. In other words, there exists an optimum mask transmittance for each D/R, from which we try to seek the feasible way of extension to the lower k1.
We will cover the EL(Exposure Latitude), the MEEF(Mask Error Enhancement Factor), and also discuss an interesting behavior of the N-M offset in utilizing high transmittance att.PSM in the low k1 node. We used the att.PSM of 20% transmittance, as a special case experiment, to investigate the effect of high transmittance around 0.3k1 lithography. This study may facilitate the application of high transmittance att.PSM to the lower k1 and contribute to extending the lifetime of optical lithography.
In low k1 optical-lithography generation, there is a non- linear amplification of mask critical dimension (CD) error during image transferring on a wafer. This error factor is called mask error enhancement factor (MEEF). In ArF system, it is premature to use commercialized simulation softwares and ArF resists. To evaluate the real resist system, we made a simple model that uses aerial images. Through the simulation, we calculated MEEFs for 180nm and 130nm line/space pairs in KrF resist system and compared them with experimental MEEFs to obtain the resist blur that satisfies the current experimental MEEFs. With a current KrF resist system, the resist blur is ~0.05 micrometers . In case of ArF resist system, the resist blur is a more important factor in MEEF and must be suppressed to lower than 0.05 micrometers to meet the proper process margin.