In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most
powerful candidate for patterning. So It has being studied to overcome the several issues such as source
power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution,
LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on.
For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so
far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography
and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for
3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately,
EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit
high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result.
Therefore it needs a lot of efforts to improve and compete against double patterning.
The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we
will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several
methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with
that of double patterning in terms of CD uniformity and pattern profile.
In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches
to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning
technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both
stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In
terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal
lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process
stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x
nm hole patterning process using double patterning technology combined with negative tone development (NTD).
Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD
with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be
discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through
NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be
Contact hole patterning is more difficult than line/space patterning as mask error factor is higher in contact hole
patterning which has 2-dimensional patterns. As the industry moves towards 40nm node and beyond, the challenges
associated with contact hole having a manufacturable process window have become increasingly difficult. Current
1.35NA ArF lithography is capable of printing 50nm contact hole with a stable process window at best. Conventional
contact hole patterning processes such as resist reflow and RELACS are no longer able to be used for half-pitch 40nm
contact hole pattern because we have to shrink not only hole diameter but also pattern pitch. In this paper, we will
demonstrate and compare the patterning performance of the mesh patterning processes including litho-etch-litho-etch, cap freezing and self freezing process.