In this paper, flexible coplanar top-gate p-type SnO TFTs are demonstrated. The TFT performance was optimized by adjusting the post-deposition annealing temperature of the SnO channel. The on/off current ratio of the TFT first improves and then degrades as the channel annealing temperature increases. With an optimized annealing temperature of 175C, the flexible SnO TFT exhibits a field-effect mobility of 0.71 cm2/V-s, threshold voltage of 5.2 V, subthreshold swing of 1.6 V/decade, and on/off current ratio of 1.6 x 103. The gate-bias stress stability of the optimized TFT was then investigated. When the TFT is at flat state, the threshold voltage shifts after bias-stressed at +10 V and -10 V for 10000 s are 0.2 V and nearly 0 V, respectively. The electrical stability degrades slightly when the TFT is subjected to both mechanical tensile and compressive strains. At a compressive strain of 0.25%, the threshold voltage shifts increase to 0.8 V and -0.3 V for positive and negative bias stress, respectively. At a tensile strain of 0.25%, the corresponding values are 0.7 V and -0.2 V. Compared with unpassivated bottom-gate SnO TFTs, the gate-bias stress stability is greatly improved.
Ambient contrast ratio (A-CR) is a critically important characteristic for mobile displays. For transmissive and emissive displays (such as liquid crystal display, light-emitting diode, and organic light-emitting diode), A-CR decreases dramatically as the ambient light increases, which degrades the image quality, especially for outdoor applications. Moth-eye-like structure greatly reduces the surface reflection and improves A-CR. For a touch panel display, the surface should be robust enough to resist possible mechanical scratches and to self-clean possible contaminations from fingerprints and dusts.
In this paper, we demonstrate the moth-eye-like structure fabricated on a hard-coating layer with additional surface treatment for self-cleaning property upon the flexible film. By laminating the film unto a display device, the luminous reflectance is reduced to ~0.23%, which improves the A-CR by ~4X under the sun. Note that although the surface reflection is reduced, the haze remains negligible, implying that the image quality is not blurred. The nanostructure was fabricated on the hard-coating layer which is typically used as the protective film of the mobile display and hence it is anti-scratched. Typically, nanostructure exhibits hydrophobic and olephobic properties. With suitable surface treatment by amphiphilic molecules, such characteristics are further improved with excellent self-cleaning properties. Besides, our nanostructured hard-coating film can be fabricated on different flexible films, such as TAC and PET, which means this broadband antireflection film can be used for flexible displays.
Key technical issues of flexible stainless steel foil substrates are addressed for OLED display backplane
applications. Surface roughness and corresponding planarization layer technology development will be the major factors
for the stainless steel foil substrates to be used for commercial applications. Promising candidates for the planarization
layer materials are reviewed and some of the properties are addressed. In addition, if the substrate is sustained to a
constant voltage for guaranteed circuit operation, capacitive coupling through the insulation and planarization dielectric
layer, from the conductive substrate to the electrode and circuit elements on it, is also carefully analyzed for panel
design and operation. Especially for large size high-resolution display applications, low k and thick planarization layer
should be used.
Our motivation is to realize CMOS on plastic foil. We report the development of thin film transistors (TFTs) made of nanocrystalline silicon (nc-Si:H). nc-Si:H is compatible with present a-Si:H thin film technology. Because of the structural evolution of nc-Si:H with film thickness, it requires extensive experimentation with device geometry. For comparison we fabricate TFTs in (a) conventional coplanar top-gate, top-source/drain geometry and (b) staggered top-gate, bottom source/drain geometry. A seed layer is introduced in the latter case serves to develop the crystallinity of the intrinsic channel layer. While the coplanar geometry provides the shortest carrier path in the most crystalline channel region, the inverted staggered geometry ensures that the active channel is formed in the last-to-grow nc-Si:H layer, and also avoids exposure of the channel to reactive ion etching (RIE). The highest process temperature is 150°C. Both intrinsic and doped nc-Si:H layers are grown by plasma-enhanced chemical vapor deposition with an excitation frequency of 80MHz. Present p-channel TFTs reach a hole field-effect mobility of ~ 0.2 cm2V-1s-1 in the staggered geometry, and an electron field-effect mobility of ~ 40 cm2V-1s-1 in both geometries. These results suggest that directly deposited nc-Si:H is an attractive candidate material for CMOS capable electronics on plastic substrates.