Mr. I. Hsing Huang Profile

I. Hsing Huang

Technical Manager at United Microelectronics Corp

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Publications (9)

Proceedings Article | 10 May 2005 Paper

The performances of different overlay mark types at 65nm node on 300-mm wafers

H. Tseng, Ling-Chieh Lin, I. Huang, Benjamin Lin, Chin-Chou Huang, Chien-Jen Huang

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598424

KEYWORDS: Overlay metrology, Chemical mechanical planarization, Metrology, Semiconducting wafers, Tungsten, Optical alignment, Manufacturing, Metals, Image processing, Optical design

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The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations. Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.

Proceedings Article | 4 May 2005 Paper

Global planarization of gap-filling process for low-k dual damascene applications

Ruei Hung Hsu, I. Huang, Ling Chieh Lin, Benjamin Szu-Min Lin

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.600408

KEYWORDS: Coating, Etching, Semiconducting wafers, Lithography, Photoresist materials, Optics manufacturing, Optical lithography, Copper, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 28 May 2004 Paper

Specification of the phase angle of a 6% attenuated PSM mask used in ArF lithography

Ching-Hsu Chang, Jochen Schacht, Benjamin Lin, Kuei-Chun Hung, I. Hsuing Huang

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535167

KEYWORDS: Critical dimension metrology, Photomasks, Image transmission, Reticles, Lithography, Phase shifts, Scanning electron microscopy, Binary data, Monochromatic aberrations, Transmittance

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Proceedings Article | 28 May 2004 Paper

Extension of ArF lithography for poly gate patterning of 65nm generation and beyond

Shu-Hao Hsu, Shu-Ping Fang, I. Hsuing Huang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534641

KEYWORDS: 193nm lithography, Lithography, Line edge roughness, Optical lithography, Chromium, Coherence (optics), Image processing, Resolution enhancement technologies, Photoresist materials, Optical proximity correction

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Proceedings Article | 14 May 2004 Paper

Optimization of resist shrink techniques for contact hole and metal trench ArF lithography at the 90-nm technology node

Christine Wallace, Jochen Schacht, I Huang, Ruei Hsu

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.534610

KEYWORDS: Photoresist processing, Critical dimension metrology, Glasses, Lithography, Semiconducting wafers, Etching, Line edge roughness, Scanning electron microscopy, Metals, Reticles

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Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.

Proceedings Article | 17 December 2003 Paper

Implementing AAPSM in 90-nm product with practical image imbalance correction

Benjamin Lin, Shu-hao Hsu, I. H. Huang, Kunyuan Chen, Frank Hsieh, Tony Hsu, Hua-Yu Liu, Armen Kroyan, Freeman Hsu, Jason Huang

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518029

KEYWORDS: Photomasks, Semiconducting wafers, Quartz, Optical proximity correction, Binary data, Phase shifts, Reticles, Neodymium, Optical lithography, Manufacturing

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Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.

Proceedings Article | 28 August 2003 Paper

Practical approach for AAPSM image imbalance correction for sub-100-nm lithography

Hung Lin Cho, Shu Yi Lin, Frank Hsieh, Armen Kroyan, Hua-Yu Liu, Jason Huang, Shu-Hao Hsu, I-Hsiung Huang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504393

KEYWORDS: Photomasks, Chromium, Critical dimension metrology, Manufacturing, Lithography, Semiconducting wafers, Reticles, Scanning electron microscopy, Optical proximity correction, Image resolution

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Proceedings Article | 30 July 2002 Paper

Contact hole photo process improvement by multiple exposures with matched illumination settings

Yeong-Song Yen, I-Hsiung Huang, Jiunn-Ren Huang, Kuei-Chun Hung, Chi-fa Ku, Ching-Hsu Chang, Cheng Fang, Paul Yen

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474540

KEYWORDS: Photomasks, Optical lithography, Semiconducting wafers, Lithographic illumination, Lithography, Resolution enhancement technologies, Image processing, Finite element methods, Microelectronics, Printing

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Proceedings Article | 14 September 2001 Paper

Novel multiple resist patterning stacks for dual-damascene interconnection and resolution-enhanced patterns

I-Hsiung Huang, Jiunn-Ren Huang, Yi-Fang Cheng, Kuei-Chun Hung, S. Chien

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435727

KEYWORDS: Etching, Photoresist processing, Optical lithography, Photomasks, Lithography, Optical proximity correction, Copper, Double patterning technology, Resolution enhancement technologies, Resistance

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Showing 5 of 9 publications

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