In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM) allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.
In recent technology node manufacturing processes, on-product overlay (OPO) is becoming increasingly more important. In previous generations, the optimization of the total measurement uncertainty (TMU) itself was sufficient. However, with the use of modern technologies, target asymmetry-related measurement inaccuracy became a significant source of error, requiring new methods of control. This paper presents a machine learning (ML) based algorithm that reduces inaccuracy in misregistration measurements of the after-develop inspection (ADI) optical overlay (OVL). The algorithm relies on numerous features that were extracted from the OVL tool camera images, accuracy metrics derived from OVL computation, and other metadata. It is trained to estimate OVL measurement inaccuracy and produce corrected OVL per site. The ground truth of the ML model can include either internal or external OVL values. In the former case, the model is trained using wafer modeling errors (a.k.a. residuals), implying that these are a good indicator of target inaccuracy, which is a commonly used assumption. In the latter case, the model is trained using external overlay as the reference. If an accurate external reference overlay measurement exists, this option can be the most accurate. In both cases, the algorithm produces corrected OVL values. This study shows that for both ground truth options, the suggested method reduces inaccuracy and wafer modeling residuals in ADI optical OVL metrology measurements. The results were obtained by experimenting on production wafers from DRAM critical layers at SK Hynix. All the measurements were taken using an imaging-based overlay (IBO) technique and were validated by scanning electron microscope (SEM) measurements of the same wafers.
To support the manufacturing of DRAM semiconductors for next and future nodes, there is a constant need to reduce the overlay fingerprints. In this paper we evaluate algorithms which are capable of decoupling wafer deformation from mark deformation and extrapolation effects. The algorithms enable lithography tools to use only the wafer deformation component in the alignment feedforward correction. Therefore improving the (wafer to wafer) overlay. First results will be shared showing improvement of wafer to wafer variation in high-volume manufacturing environment.
With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter, driving requirements for on-product overlay performance below 2.5nm and CD uniformity requirements below 0.8nm. Achieving such performance levels will not only need performance optimization of individual tools but a holistic optimization of all process steps. This paper reports on the first step towards holistic optimization – co-optimized performance control of scanner and etch tools. In this paper we evaluate the use of scanner and etcher control parameters for improvement of after final etch overlay and CD performance. The co-optimization of lithography and etch identifies origins of the variabilities and assigns corrections to corresponding tools, handles litho-etch interactions and maximizes the correction capability by utilizing control interfaces of both scanner and etch tools in a single control loop. The product aims to improve total variability measured after etch as well as fingerprint matching between tools. For CD control we co-optimize the dose corrections on the lithography tool with the temperature corrections on the etcher. This control solution aims to correct CD variabilities originating at deposition, lithography and etcher. For overlay we co-optimize the overlay inter and intra-field grid interfaces on the scanner with the wafer edge ring height compensation on the etcher. The evaluation of both CD and overlay control solutions is performed for the 2xnm DRAM node of SK hynix DRAM group. YieldStar in-device metrology after core etch was used for CD control. On wafer verification showed an improvement of 23% of the total CD variation. In-device metrology after final etch was user for overlay control. Evaluation showed 35% improvement in total overlay variability due to scanner-etch co-optimization.