The trend toward narrower line widths in the manufacture of integrated circuits has put an increasing burden on contamination control in every aspect of semiconductor fabrication. For a deep sub micrometer device, metal contamination appearing on the device can cause fatal problems including increasing the leakage current at the p-n junction, decreasing the breakdown voltage of oxide. Many lithographic defects have been known and evaluated, however, the effects of metallic impurity (Zn) in solvent are seldom reported during lithography process. Solvents are component material for Photoresist and have been used for prewet, strippers, EBR, rinse and so on during photolithography process. Lithography plays a very important role because it is applied repeatedly onto the wafer surface during device manufacturing. Unfortunately, pattern lifting happened to well formation layer wafers that were reworked on a normal iline litho process after stripping the Photoresist with solvent (PGMEA). We also detected blocked pattern defect at 0.18 CMOS gate pattern coated with DUV resist applied solvent prewet step after BARC coating. From various investigations, we could know that pattern lifting and blocked defect were derived from solvent (PGMEA).
In this paper, we show mechanism of adhesion fails and blocked defect happened by metallic impurity Zn in solvent during solvent rework and prewet on organic BARC film. It shows that proper control of metallic impurities in thinner is an important item in FAB.
Critical Dimension of gate pattern in CMOS process is the most important parameter for transistor performance and Organic BARC is generally used for controlling gate CD by reducing the substrate reflectivity. After gate etch process, small poly-silicon block defects are formed and those are derived from BARC material. After S/W nitride deposition and etch process the defects become larger and formed block defects of Belly Button type. These “Belly Buttons” are blocking the active area of transistor, make the device characteristic worse and lead to yield loss. To reduce Belly Buttons, we have evaluated various BARC resist filtration methods including new filtration material and smaller size filter in 0.18~0.35 μm CMOS gate pattern process. It was possible to reduce Belly Buttons dramatically using optimized resist filtration method and we finally got the yield up.
The resist cracking phenomenon in hole pattern on TEOS oxide has been investigated widely. We found from various tests that the root cause is just poor adhesion between resist and TEOS oxide and better adhesion process can skip additional process like a plasma treatment to avoid resist cracking. In this work, we show the relations between adhesion and prime process and finally suggest the way to improve adhesion, which will be more critical to lithography process below 130nm because of easier pattern collapse due to high aspect ratio and narrow width.
In low k1 lithography, reticle quality decides the process capability. Therefore, we must minimize CD errors on the reticle plate. Double Step process (DS process) is a unique method to improve CD uniformity of line patterns on the active region of poly layer reticle. In DS process, poly layer design is divided into the active region and the non-active region. And then, these two regions are processed individually. By using this procedure, pattern density variation across the reticle plate is reduced when making line patterns on the active region. As a result, the loading effect of the dry etching process reduced, and CD uniformity of these patterns can be improved. Using this technique of reticle fabrication, CD uniformity could be improved. Particularly, the range of CD variation of line patterns in logic cells was drastically reduced from 29nm to 20nm.
We investigated the printability of various OPC patterns with different sizes and densities for mask technology below 0.13 micrometers design rule using CAR and 50kV e-beam system. Because of high resolution characteristics of CAR process with high acceleration voltage system, we obtained OPC printability of 0.12 micrometers even in scattering bar type and excellent pattern fidelity. How to design to get required OPC pattern, design guide was considered in this work and discussed the applicability of CAR process to practical manufacturing of OPC masks of 0.13 micrometers design rule or less.
The Verimask inspection standard is widely used to qualify inspection systems due to its simplicity, ease of use in a production environment, and readily understandable defect sensitivity table. The Verimask's major drawback is that it does not characterize the runability of an inspection system. Runability refers to the system's ability to inspect various pattern types, a critical characteristic of inspection systems used for mask manufacturing. Comprehensive inspection system capability evaluation should include both sensitivity and runability tests. Other inspection test masks suffer the same shortcoming of Verimask, providing simple sensitivity analysis without runability evaluation. The Universal Inspection Standard was developed to expand the Verimask's sensitivity test and to provide a runability test. The UIS runability module contains several typical industrial feature types at multiple technology nodes. We have used UIS to evaluate and benchmark inspection system and algorithms. Future UIS versions will be available with different feature and defect types to keep pace with inspection system development. In short, UIS provides a means to quantify an inspection system's runability in addition to the traditional sensitivity evaluation.
We have investigated the performances of positive Chemically Amplified Resist (CAR) with High Acceleration Voltage System on mask fabrication, widely. As we had expected, the resolution and pattern fidelity both after development and after etching were improved dramatically, because of its high contrast and good dry etching durability. As a result, practical resolution limitation was 0.2 micrometer and CD linearity for 0.2 micrometer to approximately 1.0 micrometer pattern range was 0.034 micrometer with Proximity Effect Correction (PEC). We obtained CD uniformity of 31 to approximately 55 nm, to 120 X 120 mm<SUP>2</SUP> area.
In order to develop 1 G bit DRAM of 0.18 micrometers design rule, it is required to generate 0.2 micrometers contact hole patterns with local DOF over 1.0 micrometers . One of good candidates is DUV attenuated phase shift mask (PSM), which improves the lithographic process margin such as depth of focus (DOF), especially in contact hole patterns due to edge enhancement effect. In the case of DUV attenuated PSM, the optimum condition for contact hole patterns near 0.2 micrometers has been investigated by simulations and experiments using chromium- based attenuated PSM with the transmittance of 6% at 248 nm wavelength. We obtained local DOF of 1.2 micrometers for 0.2 micrometers contact hole of 1 G bit DRAM with printing bias of -0.046 micrometers using KrF laser system (0.31 (sigma) , 0.55 NA). We evaluated the characteristics of contact hole with various duty ratios and defect printability using programmed defects.
An attenuated phase shift mask (PSM) is the most promising candidate for the high volume production lithography process among the various PSM types. It has been shown that attenuated PSM improves the lithographic performance such as depth of focus, especially in contact window by its edge enhancement. In this paper, the side lobe effect that restricts the lithographic performance of attenuated PSM and the light intensity distribution have been examined on changing the pattern density and the transmittance by experimental and simulation. The side lobe effect caused by proximity effect is very severe when pitch sizes are in the range of 0.7-0.9 micrometers for 0.35-0.45 micrometers contact hole on mask and it is enlarged by defocus exposure condition. The side lobe effect in this range of pitch size may forms the additional pattern in wafer, which restricts the application of attenuated PSM. The side lobe effect can be removed by additional pattern positioning at the center of four contact hole patterns, but simulation result of Exposure-Defocus tree (E-D tree) shows that lithographic performance of attenuated PSM is decreased by an auxiliary pattern. In the application of attenuated PSM in dense pattern, the relation between performance and side lobe effect is mutually contradictory.
The optical lithography is extending its life by combining high numerical aperture (NA) optics and shorter wavelength. The shorter wavelength lithography has required the new developments of related technologies. In particular, DUV resists require an entirely different resist chemistry. Much progress has been demonstrated in the field of transparent chemically amplified resists with high sensitivity. However, this DUV lithography ((lambda) equals 248 nm) has been delayed for mass production due to their limitations, such as (i) delay time effects, (ii) high cost ownership due to expensive resist materials and laser maintenance, and (iii) critical dimension (CD) variation over topography caused by multireflection of topographic features. On the other hand, i- line lithography ((lambda) equals 365 nm) has apparently been applied to 64M DRAM of 0.35 micrometers design rule, and attempted to 0.30 micrometers technology which corresponds to 2nd generation 64M DRAM or 1st generation 256 M DRAM. It might be achieved by combination of off-axis illumination (OAI), phase shift mask (PMS) and advanced resist process technique of i-line lithography. Therefore, i-line lithography can be more practical method rather than DUV lithography for the mass production. In this paper, we have optimized the i-line lithographic techniques for the various pattern shape and density for 0.30 micrometers design rule. Optimum duty ratio was tried to find for line and space, contact hole patterns. The basic rule is to keep the minimum Cr width over 0.30 micrometers mask. OAI have been applied to get higher contrast of line and space, and even contact hole patterns, and achieve good pattern fidelities of island patterns. By the implementation of OAI, process latitudes were greatly improved compared to that of conventional techniques. In order to optimize the process over the actual topography, optimum numerical aperture (NA) and aperture of the OAI were selected. In conclusion, 0.30 micrometers design rule device was successfully fabricated by optimizing the advanced i-line lithographic techniques.