Overlay metrology performances highly depend on the detailed design of the measured target. Hence performing simulations is an essential tool for optimizing target design. We demonstrate for scatterometry overlay (SCOL) three key factors which enable consistency in ranking between simulated and measured metrology performance for target design. The first factor, to enable high fidelity simulations for the purpose of target design, is stack and topography verification of model inputs. We report in detail the best known film metrology methods required to achieve model integrity. The second factor is the method of calculation of metrology performance metrics based on target cell reflectivities from electro-magnetic (EM) simulations. These metrics enable ranking of different designs, and subsequent choice of the best performing designs among all simulated design options, the ranking methodology being the third factor. We apply the above steps to a specific stack, where five different designs have been considered. Simulated versus measured values are compared. A good agreement between simulation and measurement is achieved.
Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.
Computational metrology target design requires both an accurate metrology simulation engine and an accurate geometric model. This paper deals with the later. Optical critical dimension metrology and cross-section SEM are demonstrated as two useful methods of geometric model verification with differing capabilities. Specifically, a methodology is proposed which allows the metrology engineer to quantify the level of accuracy required by the model as a function of the tolerable uncertainty in the prediction of metrology performance metrics. The methodology identifies a subset of model parameters which need to be verified enabling the metrology engineer to invest the minimum effort in stack and topography verification which will lead to performing target designs on the first design round.
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (<strong>OVL</strong>) targets and actual device overlay error. In this study, we introduce the concept of <strong>Device Correlated Metrology</strong> (<strong>DCM</strong>), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical <strong>OVL</strong> target with a device mimicking <strong>CD-SEM</strong> (Critical Dimension – Scanning Electron Microscope) target. The hybrid <strong>OVL</strong> target is designed to accurately represent the process influence found on the real device. In the general case, the <strong>CD-SEM</strong> can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of <strong>CD-SEM</strong> measurement uncertainty. Direct <strong>OVL</strong> measurements by <strong>CD-SEM</strong> show excellent correlation with optical <strong>OVL</strong> measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based <strong>OVL</strong> metrology methods using <strong>AIM</strong> or <strong>AIMid OVL</strong> targets, and scatterometry-based overlay methods such as SCOL (Scatterometry <strong>OVL</strong>). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.
One of the main challenges related to the growing number of Litho layers and most specifically to Multi Patterning, is the ability to align to many layers at once. In the past things were simple, the alignment tree was set so that every layer aligns to one layer and at the most is measured versus two layers, such as contact to poly and Isolation. Today, even at the 20 nm node there are double and triple patterning for critical layers such as Isolation, poly, contact and Metal 1. This forces a much more complex alignment tree and Overlay (OVL) measurement. Layers are sometimes aligned to an average of previous layers, to different layers at different orientations and disposition is done based on several measurements. This growing challenge increases the number of Overlay measurements significantly, increases the target area and present the need to make many measurement from different layers consistent. Another challenge is the increased number of recipes and the need for flexible alignment tree scheme during development. These challenges are addressed by Multi layer targets such as Triple AIM, Multilayer AIMid and the Blossom and micro-Blossom targets where alignment marks from multiple patterning steps and layers were densely populated. A single OVL reading is calculated by the metrology tool on a selected pair or multiple pair average<sup>1</sup>. Here we propose the Multi-Layer measurement that provides an additional degree of metrology and solution to these challenges: in one measurement several overlay results are achieved, the results are always self-consistent. It allows at the same measurement grab to look back and disposition previous layers after their processing was completed. It allows a flexible alignment tree without the need to add or change targets, even during ramp and production. It reduces the number of recipes that need to be created and managed. And it also reduces significantly the area needed for the targets. In this paper we will show recent results from IMEC, on Back-End (BE) stack of four layers including one double patterning layer. We compared several target sizes, showing that such a target can fit within the Indie requirements of 10x10 μm. Results show that there is not a lot of need to compromise on performance in order to get good Multi-Layer measurements. Eventually we will describe process compatible targets which are needed more in the Front End (FE) layers. Looking forward at the increased complexity needed for future nodes and multiple pitch splitting lithography, it is encouraging to see that for Overlay we can simplify metrology instead of making it follow the complexity trend.
Overlay control is one of the most critical areas in advanced semiconductor processing. Maintaining
optimal product disposition and control requires high quality data as an input. Outliers can contaminate lot
statistics and negatively impact lot disposition and feedback control. Advanced outlier removal methods
have been developed to minimize their impact on overlay data processing. Rejection methods in use today
are generally based on metrology quality metrics, raw data statistics and/or residual data statistics.
Shortcomings of typical methods include the inability to detect multiple outliers as well as the unnecessary
rejection of valid data. As the semiconductor industry adopts high-order overlay modeling techniques,
outlier rejection becomes more important than for linear modeling. In this paper we discuss the use of
robust regression methods in order to more accurately eliminate outliers. We show the results of an
extensive simulation study, as well as a case study with data from a semiconductor manufacturer.